Table 165. Adc Global Register Map - ST STM32G4 Series Reference Manual

Analog-to-digital converters (ADC)
20.7.3 ADC x Common regular data register for dual mode (ADCx_CDR)
(x=1/2 or 3/4/5)
Address offset: 0x0C (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000
One interface controls ADC1 and ADC2, while the other interface controls ADC3, ADC4 and
ADC5.
31 30 29 28
r r r
15 14 13 12
r r r
Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC
Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC.
20.7.4 ADC register map
The following table summarizes the ADC registers.
Offset
0x000 - 0x0FC
0x100 - 0x1FC
0x200 - 0x2FC
0x300 - 0x30C
680/3748
27 26 25
r r r r
11 10 9
r r r r
In dual mode, these bits contain the regular data of the slave ADC. Refer to
Dual ADC modes.
The data alignment is applied as described in
offset (ADC_DR, OFFSETy, OFFSETy_CH,
In dual mode, these bits contain the regular data of the master ADC. Refer to
Section 20.4.30: Dual ADC
The data alignment is applied as described in
offset (ADC_DR, OFFSETy, OFFSETy_CH,
In MDMA=0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains
MST_ADC_DR[7:0].

Table 165. ADC global register map

24 23 22
RDATA_SLV[15:0]
r r r
8 7 6
RDATA_MST[15:0]
r r r
Section : Data register, data alignment and
ALIGN))
modes.
Section : Data register, data alignment and
ALIGN))
Register
Master ADC1/ADC3
Slave ADC2/ADC4
Reserved/single ADC5
Master and slave ADCs common registers
RM0440 Rev 1
21 20 19 18
r r r r
5 4 3 2
r r r r
RM0440
17 16
r r
1 0
r r
Section 20.4.30: