ST STM32G4 Series Reference Manual page 919

Advanced arm-based 32-bit mcus

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HRTIM master timer interrupt status register (HRTIM_MISR)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 MUPD: Master update interrupt flag

This bit is set by hardware when the master timer registers are updated.

0: No master update interrupt occurred

1: Master update interrupt occurred

Bit 5 SYNC: Sync input interrupt flag

This bit is set by hardware when a synchronization input event is received.

0: No sync input interrupt occurred

1: Sync input interrupt occurred

Bit 4 MREP: Master repetition interrupt flag

This bit is set by hardware when the master timer repetition period has elapsed.

0: No master repetition interrupt occurred

1: Master repetition interrupt occurred

Bit 3 MCMP4: Master compare 4 interrupt flag

Refer to MCMP1 description

Bit 2 MCMP3: Master compare 3 interrupt flag

Refer to MCMP1 description

Bit 1 MCMP2: Master compare 2 interrupt flag

Refer to MCMP1 description

Bit 0 MCMP1: Master compare 1 interrupt flag

This bit is set by hardware when the master timer counter matches the value programmed in the

master compare 1 register.

0: No master compare 1 interrupt occurred

1: Master compare 1 interrupt occurred

RM0440 Rev 1

High-resolution timer (HRTIM)

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