Power Port D Pull-Up Control Register (Pwr_Pucrd); Power Port D Pull-Down Control Register (Pwr_Pdcrd) - ST STM32G4 Series Reference Manual

Power control (PWR)
31 30 29
Res. Res. Res. Res.
15 14 13
PD15 PD14 PD13 PD12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PDy: Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.
5.4.14

Power Port D pull-up control register (PWR_PUCRD)

Address offset: 0x38.
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31 30 29
Res. Res. Res. Res.
15 14 13
PU15 PU14 PU13 PU12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PUy: Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.
5.4.15

Power Port D pull-down control register (PWR_PDCRD)

Address offset: 0x3C.
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
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28 27 26 25
Res. Res. Res.
12 11 10 9
PD11 PD10 PD9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
PU11 PU10 PU9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
PD8 PD7 PD6
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
PU8 PU7 PU6
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PD5 PD4 PD3 PD2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PU5 PU4 PU3 PU2
rw rw rw rw
RM0440
17 16
Res. Res.
1 0
PD1 PD0
rw rw
17 16
Res. Res.
1 0
PU1 PU0
rw rw