ST STM32G4 Series Reference Manual page 719

RM0440
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC2DHRB[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software. They specify 12-bit data for DAC channel2 when the DAC
operates in DMA Double data mode.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software. They specify 12-bit data for DAC channel2.
21.7.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2)
This register is available only on dual-channel DACs. Refer to
implementation.
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
rw rw rw
Bits 31:20 DACC2DHRB[11:0]: DAC channel2 12-bit left-aligned data B
Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
Bits 3:0 Reserved, must be kept at reset value.
21.7.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2)
This register is available only on dual-channel DACs. Refer to
implementation.
27 26 25
11 10 9
rw rw rw
27 26 25
DACC2DHRB[11:0]
11 10 9
DACC2DHR[11:0]
rw rw rw rw
These bits are written by software. They specify 12-bit data for DAC channel2 when the
DAC operates in Double data mode.
These bits are written by software which specify 12-bit data for DAC channel2.
24 23 22
DACC2DHRB[11:0]
8 7 6
DACC2DHR[11:0]
rw rw rw
24 23 22
8 7 6
rw rw rw
RM0440 Rev 1
Digital-to-analog converter (DAC)
21 20 19 18
5 4 3 2
rw rw rw rw
Section 21.3: DAC
21 20 19 18
Res. Res.
5 4 3 2
Res. Res.
rw rw
Section 21.3: DAC
17 16
1 0
rw rw
17 16
Res. Res.
1 0
Res. Res.
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