Table 297. Timx_Arr Register Change Dithering Pattern; Table 298. Dma Request - ST STM32G4 Series Reference Manual

RM0440
The auto-reload and compare values increments are spread following specific patterns
described in the
distributed as evenly as possible and minimize the overall ripple.
-
LSB value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
30.3.6 UIF bit remapping
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update
Interrupt Flag UIF into the timer counter register's bit 31 (TIMxCNT[31]). This allows to
atomically read both the counter value and a potential roll-over condition signaled by the
UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions
caused for instance by a processing shared between a background task (counter reading)
and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.
30.3.7 TIM6/TIM7 DMA requests
The TIM6/TIM7 can generate a single DMA request, as shown in
DMA acronym
TIM6_UP
TIM7_UP
Table 297 below. The dithering sequence is done to have increments

Table 297. TIMx_ARR register change dithering pattern

1 2 3 4 5
- - - - -
+1 - - - -
+1 - - - -
+1 - - - +1
+1 - - - +1
+1 - +1 - +1
+1 - +1 - +1
+1 - +1 - +1
+1 - +1 - +1
+1 +1 +1 - +1
+1 +1 +1 - +1
+1 +1 +1 - +1
+1 +1 +1 - +1
+1 +1 +1 +1 +1
+1 +1 +1 +1 +1
+1 +1 +1 +1 +1

Table 298. DMA request

DMA request
RM0440 Rev 1
PWM period
6 7 8 9
- - - -
- - - -
- - - +1
- - - +1
- - - +1
- - - +1
- - - +1
- +1 - +1
- +1 - +1
- +1 - +1
- +1 - +1
+1 +1 - +1
+1 +1 - +1
+1 +1 - +1
+1 +1 - +1
+1 +1 +1 +1
Update
Basic timers (TIM6/TIM7)
10 11 12 13 14
- - - - -
- - - - -
- - - - -
- - - - -
- - - +1 -
- - - +1 -
- +1 - +1 -
- +1 - +1 -
- +1 - +1 -
- +1 - +1 -
+1 +1 - +1 -
+1 +1 - +1 -
+1 +1 - +1 +1
+1 +1 - +1 +1
+1 +1 +1 +1 +1
+1 +1 +1 +1 +1
Table 298.
Enable control bit
UDE
15 16
- -
- -
- -
- -
- -
- -
- -
- -
+1 -
+1 -
+1 -
+1 -
+1 -
+1 -
+1 -
+1 -
1411/2083
1417