Figure 157. Dac Lfsr Register Calculation Algorithm; Figure 158. Dac Conversion (Sw Trigger Enabled) With Lfsr Wave Generation - ST STM32G4 Series Reference Manual

RM0440
The following conditions must be met to change from Double data to single data mode or
vice versa:
•
The DAC must be disabled.
•
DMAEN bit must be cleared (ENx=0 and DMAENx=0).
21.4.9 Noise generation
In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVEx[1:0] to 01". The
preloaded value in LFSR is 0xAAA. This register is updated three dac_hclk clock cycles
after each trigger event, following a specific calculation algorithm.
XOR
X
The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then transferred into the DAC_DORx register.
If LFSR is 0x0000, a '1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 158. DAC conversion (SW trigger enabled) with LFSR wave generation

dac_pclk
DHR
DOR
SWTRIG

Figure 157. DAC LFSR register calculation algorithm

12
11 10 9
0x00
6
X
8 7 6 5
12
NOR
0xAAA
RM0440 Rev 1
Digital-to-analog converter (DAC)
4
X
X
4 3 2 1
0xD55
0
X
0
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