ST STM32G4 Series Reference Manual page 955

RM0440
26.5.30 HRTIM timer x output 2 reset register (HRTIM_RSTx2R) (x = A to F)
Address offset: Block A: 0x0C8
Address offset: Block B: 0x148
Address offset: Block C: 0x1C8
Address offset: Block D: 0x248
Address offset: Block E: 0x2C8
Address offset: Block F: 0x348
Reset value: 0x0000 0000
31 30 29
EXT
UPDAT EXT EXT
EVNT1
E EVNT9 EVNT8
0
rw rw rw
15 14 13
TIM TIM TIM
EVNT4 EVNT3 EVNT2 EVNT1
rw rw rw
Bits 31:0 Refer to HRTIM_SETx1R bits description.
These bits are defining the source which forces the Tx2 output to its inactive state.
28 27 26 25
EXT EXT EXT
EVNT7 EVNT6 EVNT5
rw rw rw rw
12 11 10 9
TIM MST MST MST
CMP4 CMP3 CMP2
rw rw rw rw
24 23 22
EXT EXT EXT
EVNT4 EVNT3 EVNT2 EVNT1
rw rw rw
8 7 6
MST MST
CMP4 CMP3
CMP1 PER
rw rw rw
RM0440 Rev 1
High-resolution timer (HRTIM)
21 20 19 18
EXT TIM TIM TIM
EVNT9 EVNT8 EVNT7
rw rw rw rw
5 4 3 2
CMP2 CMP1 PER
rw rw rw rw
17 16
TIM TIM
EVNT6 EVNT5
rw rw
1 0
RESYN
SRT
C
rw rw
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