True random number generator (RNG)
Interrupt acronym
RNG
The user can enable or disable the above interrupt sources individually by changing the
mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the
individual interrupt sources can be read from the RNG_SR register.
Note:
Interrupts are generated only when RNG is enabled.
25.5
RNG processing time
The conditioning stage can produce four 32-bit random numbers every 16x
cycles, if the value is higher than 213 cycles (213 cycles otherwise).
More time is needed for the first set of random numbers after the device exits reset (see
Section 25.3.4: RNG
data is first available after either:
•
128 RNG clock cycles + 426 AHB cycles, if f
•
192 RNG clock cycles + 213 AHB cycles, if f
With f
threshold
25.6
RNG entropy source validation
25.6.1
Introduction
In order to assess the amount of entropy available from the RNG, STMicroelectronics has
tested the peripheral using German BSI AIS-31 statistical tests (T0 to T8). The results can
be provided on demand or the customer can reproduce the tests.
25.6.2
Validation conditions
STMicroelectronics has tested the RNG true random number generator in the following
conditions:
•
RNG clock rng_clk= 48 MHz (CED bit = '0' in RNG_CR register) and rng_clk = 400 kHz
(CED bit = '1' in RNG_CR register).
25.6.3
Data collection
In order to run statistical tests it is required to collect samples from the entropy source at raw
data level as well as at the output of the entropy source.
Contact STMicroelectronics if above samples need to be retrieved for your product.
796/2083
Table 198. RNG interrupt requests
Interrupt event
Event flag
Data ready flag
Seed error flag
Clock error flag
initialization). Indeed, after enabling the RNG for the first time, random
= (213 x f
)/ 64
RNG
Enable control bit
DRDY
IE
SEIS
IE
CEIS
IE
< f
AHB
≥ f
AHB
RM0440 Rev 1
Interrupt clear method
None (automatic)
Write 0 to SEIS or write
CONDRST to 1 then to 0
Write 0 to CEIS
f
AHB
------------
f
RNG
threshold
threshold
RM0440
clock
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