Table 181. Sample And Refresh Timings - ST STM32G4 Series Reference Manual

RM0440
Sample and Hold mode
In sample and Hold mode, the DAC core converts data on a triggered conversion, and then
holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer
are completely turned off between samples and the DAC output is tri-stated, therefore
reducing the overall power consumption. A new stabilization period, which value depends
on the buffer state, is required before each new conversion.
In this mode, the DAC core and all corresponding logic and registers are driven by the low-
speed clock (LSI or LSE) in addition to the dac_hclk clock, allowing to use the DAC
channels in deep low power modes such as Stop mode. The low speed clock (LSI or LSE)
must not be stopped on the fly when the Sample and Hold mode is enabled.
The sample/hold mode operations can be divided into 3 phases:
1. Sample phase: the sample/hold element is charged to the desired voltage. The
charging time depends on capacitor value (internal or external, selected by the user).
The sampling time is configured with the TSAMPLEx[9:0] bits in DAC_SHSRx register.
During the write of the TSAMPLEx[9:0] bits; the BWSTx bit in DAC_SR register is set to
1 to synchronize between both clocks domains (AHB and low speed clock) and
allowing the software to change the value of sample phase during the DAC channel
operation
2. Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are
turned off, to reduce the current consumption. The hold time is configured with the
THOLDx[9:0] bits in DAC_SHHR register
3. Refresh phase: the refresh time is configured with the TREFRESHx[7:0] bits in
DAC_SHRR register
The timings for the three phases above are in units of LSI/LSE clocks. As an example, to
configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs
assuming LSI/LSE ~32 KHz is selected:
12 cycles are required for sample phase: TSAMPLEx[9:0] = 11,
62 cycles are required for hold phase: THOLDx[9:0] = 62,
and 4 cycles are required for refresh period: TREFRESHx[7:0] = 4.
In this example, the power consumption is reduced by almost a factor of 15 versus Normal
modes.
The formulas to compute the right sample and refresh timings are described in the table
below, the Hold time depends on the leakage current.
Buffer
State
Enable
Disable
1. In the above formula the settling to the desired code value with ½ LSB or accuracy requires 10 constant
time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant time.
2. C is the capacitor in Sample and Hold mode.
SH
3. The tolerated voltage drop during the hold phase "Vd" is represented by the number of LSBs after the
capacitor discharging with the output leakage current. The settling back to the desired value with ½ LSB
error accuracy requires ln(2*Nlsb) constant time of the DAC.

Table 181. Sample and refresh timings

(1)(2)
t
SAMP
7 μs + (10*R *C )
BON SH
3 μs + (10*R *C )
BOFF SH
RM0440 Rev 1
Digital-to-analog converter (DAC)
t
(2)(3)
REFRESH
7 μs + (R *C )*ln(2*N
BON SH
3 μs + (R *C )*ln(2*N
BOFF SH
)
LSB
)
LSB
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