Figure 681. Ucpd Bmc Transmitter Architecture - ST STM32G4 Series Reference Manual

RM0440
UCPD_TXDR
register
UCPD_TX_ORDSET
register
UCPD_TX_PAYSZ
register
UCPD_CR
register
UCPD_CFG1/2/3
registers
BMC encoder
The method is defined by an IEC specification:
–
UCPD generates bits based on a simple (integral) clock divider giving all bits the same
length (excluding second order jitter issues). The half-bit time will be nominally exactly half
the bit time, and only second order effect of rising/falling edge mismatch in the SoC will
make a small deviation between high and low times for half-bits.
The field controlling the timing for a half-bit is HBITCLKDIV.
Transmitter Timing and collision avoidance
Hardware support of collision avoidance is made as a function of the half bit time for the
transmitter. Two counters are implemented:
–
–
These two counters once set correctly will generate the interframe gap.
Hard Reset in Transmitter
In order to facilitate generation of a Hard Reset, a special code of TXMODE field is used. No
other fields need to be written.
On writing the correct code, the hardware will force Hard Reset Tx under the correct
(optimal) timings with respect to an on-going Tx message, which (if still in progress) will be
cleanly terminated by truncating the current sequence and directly appending an EOP K-
Code sequence. No specific interrupt will be generated relating to this truncation event.

Figure 681. UCPD BMC Transmitter architecture

Clock domain boundary:
PClk ; UsbpdClk
Message
parameters
USB PD
Transmitter
Trigger /
State machine
Tx msg type
General
parameters
IEC 60958-1 Digital Audio Interface Part:1 General Edition 3.0 2008-09
www.iec.ch
tInterFrameGap: via IFRGAP (pre-defined value, can be altered)
tTransitionWindow: via TRANSWIN (pre-defined value, can be altered)
USB Type-C™ / USB Power Delivery interface (UCPD)
Clock domain boundary:
UsbpdClk ; Usbpd_HalfbitClk (= UsbpdClk /
HBITCLKDIV+1 )
CRC
Fixed framing
RM0440 Rev 1
BMC
4b5b
encoder
encoder
MSv45544V1
2011/2083
CC_out
CC_OEN
2040