Figure 432. Triggering Tim_Slv With Update Of Tim_Mstr; Figure 433. Triggering Tim_Slv With Enable Of Tim_Mstr - ST STM32G4 Series Reference Manual

RM0440
clock frequencies are divided by 3 by the prescaler compared to tim_ker_ck (f
f
tim_ker_ck
1. Configure TIM_mstr master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM_mstr_CR2 register).
2. Configure the TIM_mstr period (TIM_mstr_ARR registers).
3. Configure TIM_slv to get the input trigger from TIM_mstr (TS=00010 in the
TIM_slv_SMCR register).
4. Configure TIM_slv in trigger mode (SMS=110 in TIM_slv_SMCR register).
5. Start TIM_mstr by writing '1 in the CEN bit (TIM_mstr_CR1 register).
TIM_slv counter enable (CEN bit)
As in the previous example, both counters can be initialized before starting counting.
Figure 433
mode instead of gated mode (SMS=110 in the TIM_slv_SMCR register).
TIM_mst counter enable (CEN bit)
/3).

Figure 432. Triggering TIM_slv with update of TIM_mstr

tim_ker_ck
tim_mstr UEV
event
tim_mst_CNT
tim_slv_CNT
tim_slv TIF bit
shows the behavior with the same configuration as in

Figure 433. Triggering TIM_slv with Enable of TIM_mstr

tim_ker_ck
tim_mstr_CNT reset
tim_mstr_CNT
tim_slv_CNT
tim_slv_CNT reset
Tim_slv_CNT write
tim_slv TIF bit
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
FD FE FF
45
75 00
CD 00
RM0440 Rev 1
00 01
46 47
Write TIF = 0
Figure 432 but in trigger
01
E7 E8
Write TIF = 0
=
tim_cnt_ck
02
48
MSv62378V1
02
E9
EA
MSv62379V1
1255/2083
1297