Figure 362. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded) - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM2/TIM3/TIM4/TIM5)

Figure 362. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag (UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

RM0440 Rev 1

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