Figure 28. Dma Block Diagram - ST STM32G4 Series Reference Manual

Direct memory access controller (DMA)
dma1_req [1..8]
dma1_ack [1..8]
dma2_req [1..8]
dma2_ack [1..8]
Note: See Figure 28: DMA block diagram
The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
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Figure 28. DMA block diagram

DMA1
Ch 1
Ch 2
Ch 8
Arbiter
Interrupt
interface
dma1_it[1..8]
DMA2
Ch 1
Ch 2
Ch 8
Arbiter
Interrupt
interface
dma2_it[1..8]
for feature implementation.
RM0440 Rev 1
AHB master
interface
AHB slave
interface
AHB master
interface
AHB slave
interface
RM0440
MSv46687V1