Figure 522. Ccm Mode Authenticated Encryption - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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CCM processing

example). This mode is selected by writing 100 into the CHMOD[2:0] bitfield of the AES_CR

AES_IVRx (CTR0)

AES_IVRx (First block B0)

AES_KEYRx (KEY)

AES_DINR (associated

data block B1)

DATATYPE[1:0]

AES_KEYRx (KEY)

The data input to the generation-encryption process are a valid nonce, a valid payload

string, and a valid associated data string, all properly formatted. The CBC chaining

mechanism is applied to the formatted plaintext data to generate a MAC, with a known

length. Counter mode encryption that requires a sufficiently long sequence of counter blocks

as input, is applied to the payload string and separately to the MAC. The resulting ciphertext

C is the output of the generation-encryption process on plaintext P.

AES_IVRx registers are used for processing each data block, AES automatically

incrementing the CTR counter with a bit length defined by the first block B0.

shows how the application must load the B0 data.

The AES peripheral in CCM mode supports counters up to 64 bits, as specified by NIST.

describes the CCM implementation within the AES peripheral (encryption