ST STM32G4 Series Reference Manual page 107

RM0440
BANK Address
1FFFF800
1FFFF808
1FFFF810
Bank 2
1FFFF818
1FFFF820
1FFFF828
User and read protection option bytes
Flash memory address: 0x1FFF 7800
ST production value: 0xFFEF F8AA
31 30 29
IRH_ PG10_
Res.
EN Mode
r r
15 14 13
nRST_ nRST_ nRST_
Res.
SHDW STDBY STOP
r r
Bits 29:28 PG10_Mode: PG10 pad mode
Embedded Flash memory (FLASH) for category 3 devices
Table 11. Option byte organization (continued)
[63:56] [55:48]
Unused
PCROP2_STRT[14:0]
Unused
PCROP2_END[14:0]
WRP2A
Unused _END
[6:0]
WRP2B
Unused _END
[6:0]
Unused
28 27 26 25
n nSW CCMSRAM
BOOT0 BOOT0 _RST
r r r
12 11 10 9
Res. BOR_LEV[2:0]
r r r
Bit 31 Reserved, must be kept at reset value.
Bit 30 IRH_IN: Internal reset holder for PG10
0: IRH disabled
1: IRH enabled
00: Reset Input/Output
01: Reset Input only
10: Reset GPIO
11: Reset Input/Output
Bit 27 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 26 nSWBOOT0: Software BOOT0
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PB8/BOOT0 pin
[47:40] [39:32] [31:24]
Unused
Unused and
Unused and
WRP2A
Unused _STRT Unused
[6:0]
WRP2B
Unused _STRT Unused
[6:0]
SEC_
_SIZE2
24 23 22
SRAM n
DBANK
_PE BOOT1
r r r
8 7 6
r r r
RM0440 Rev 1
[23:16] [15:8]
Unused and
Unused
PCROP2_STRT[14:0]
Unused and
Unused
PCROP2_END[14:0]
WRP2A
_END Unused
[6:0]
WRP2B
_END Unused
[6:0]
Unused
21 20 19 18
Re WWDG IWGD_
BFB2
s. _SW STDBY
r r
5 4 3 2
RDP[7:0]
r r r r
[7:0]
WRP2A
_STRT
[6:0]
WRP2B
_STRT
[6:0]
SEC_
_SIZE2
17 16
IWDG_ IWDG_
STOP SW
r r
1 0
r r
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