RM0440
23.3.2
COMP pins and internal signals
The I/Os used as comparators inputs must be configured in analog mode in the GPIOs
registers.
The comparator output can be connected to the I/Os using the alternate function channel
given in "Alternate function mapping" table in the datasheet.
The output can also be internally redirected to a variety of timer input for the following
purposes:
•
Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
•
Cycle-by-cycle current control, using OCREF_CLR inputs
•
Input capture for timing measures
It is possible to have the comparator output simultaneously redirected internally and
externally.
COMP1_
INPSEL
INP
0
PA1
1
PB1
INMSEL
COMP1_
[2:0]
INM
000
001
010
011
100
DAC3_CH1
101
DAC1_CH1
110
PA4
111
PA0
23.3.3
COMP reset and clocks
The COMP clock provided by the clock controller is synchronous with the APB2 clock.
There is no COMP-dedicated clock enable control bit in the RCC controller. Reset and clock
enable bits are common for COMP and SYSCFG.
Note:
Important: The polarity selection logic and the output redirection to the port works
independently of APB clock. This allows the comparator to work even in Stop mode.
Table 188. COMPx non-inverting input assignment
COMP2_
COMP3_
INP
INP
PA7
PA0
PA3
PC1
Table 189. COMPx inverting input assignment
COMP2_
COMP3_
INM
INM
DAC3_CH2
DAC3_CH1
DAC1_CH2
DAC1_CH1
PA5
PF1
PA2
PC0
RM0440 Rev 1
COMP4_
COMP5_
INP
INP
PB0
PB13
PE7
PD12
COMP4_
COMP5_
INM
INM
1/4 V
REFINT
1/2 V
REFINT
3/4 V
REFINT
V
REFINT
DAC3_CH2
DAC4_CH1
DAC1_CH1
DAC1_CH2
PE8
PB10
PB2
PD13
Comparator (COMP)
COMP6_
COMP7_
INP
INP
PB11
PB14
PD11
PD14
COMP6_
COMP7_
INM
INM
DAC4_CH2
DAC4_CH1
DAC2_CH1
DAC2_CH1
PD10
PD15
PB15
PB12
737/2083
743
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