ST STM32G0 1 Series Reference Manual

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RM0444

Reference manual

STM32G0x1 advanced Arm

-based 32-bit MCUs

Introduction

This reference manual complements the datasheets of the STM32G0x1 microcontrollers,

providing information required for application and in particular for software development. It

pertains to the superset of feature sets available on STM32G0x1 microcontrollers.

For feature set, ordering information, and mechanical and electrical characteristics of a

particular STM32G0x1 device, refer to its corresponding datasheet.

For information on the Arm

Cortex

-M0+ core, refer to the Cortex

-M0+ technical

reference manual.

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Summary of Contents for ST STM32G0 1 Series

Page 1 -M0+ Technical Reference Manual”, available from: http://infocenter.arm.com ® • PM0223 programming manual for Cortex -M0+ core • STM32G0x1 datasheets • AN2606 application note on booting STM32 MCUs a. Available on STMicroelectronics website www.st.com November 2020 RM0444 Rev 5 1/1390 www.st.com...
Page 2: Table Of Contents
Contents RM0444 Contents Documentation conventions ....... . . 53 General information ......... 53 List of abbreviations for registers .
Page 3 RM0444 Contents 3.5.2 FLASH proprietary code readout protection (PCROP) ... . . 94 3.5.3 FLASH write protection (WRP) ....... 96 3.5.4 Securable memory area .
Page 4 Contents RM0444 Power supplies ..........119 4.1.1 ADC and DAC reference voltage .
Page 5 RM0444 Contents 4.4.17 Power Port E pull-down control register (PWR_PDCRE) ..156 4.4.18 Power Port F pull-up control register (PWR_PUCRF) ... . . 156 4.4.19 Power Port F pull-down control register (PWR_PDCRF) .
Page 6 Contents RM0444 5.4.8 Clock interrupt clear register (RCC_CICR) ..... 189 5.4.9 I/O port reset register (RCC_IOPRSTR) ..... . . 190 5.4.10 AHB peripheral reset register (RCC_AHBRSTR) .
Page 7 RM0444 Contents 6.7.2 CRS configuration register (CRS_CFGR) ..... . 227 6.7.3 CRS interrupt and status register (CRS_ISR) ....228 6.7.4 CRS interrupt flag clear register (CRS_ICR) .
Page 8 Contents RM0444 7.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to F) ..........244 7.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to F) .
Page 9 RM0444 Contents 8.1.28 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) ..264 8.1.29 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26) ..264 8.1.30 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27) ..264 8.1.31 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) .
Page 10 Contents RM0444 10.4 DMA functional description ........278 10.4.1 DMA block diagram .
Page 11 RM0444 Contents 11.6.3 DMAMUX request line multiplexer interrupt clear flag register (DMAMUX_CFR) ......... 309 11.6.4 DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) .
Page 12 Contents RM0444 13.5.13 EXTI CPU wakeup with event mask register (EXTI_EMR1) ..332 13.5.14 EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) ..333 13.5.15 EXTI CPU wakeup with event mask register (EXTI_EMR2) ..333 13.5.16 EXTI register map .
Page 13 RM0444 Contents 15.3.13 Timings ..........357 15.3.14 Stopping an ongoing conversion (ADSTP) .
Page 14 Contents RM0444 15.12.4 ADC configuration register 1 (ADC_CFGR1) ....387 15.12.5 ADC configuration register 2 (ADC_CFGR2) ....391 15.12.6 ADC sampling time register (ADC_SMPR) .
Page 15 RM0444 Contents 16.7 DAC registers ..........424 16.7.1 DAC control register (DAC_CR) .
Page 16 Contents RM0444 17.3.3 VREFBUF register map ........444 Comparator (COMP) .
Page 17 RM0444 Contents 19.6 RNG entropy source validation ....... 467 19.6.1 Introduction .
Page 18 Contents RM0444 20.7.2 AES status register (AES_SR) ......513 20.7.3 AES data input register (AES_DINR) ......514 20.7.4 AES data output register (AES_DOUTR) .
Page 19 RM0444 Contents 21.3.16 Using the break function ........560 21.3.17 Bidirectional break inputs .
Page 20 Contents RM0444 21.4.19 TIM1 capture/compare register 4 (TIM1_CCR4) ....608 21.4.20 TIM1 break and dead-time register (TIM1_BDTR) ......... . . 608 21.4.21 TIM1 DMA control register (TIM1_DCR) .
Page 21 RM0444 Contents 22.3.19 Timer synchronization ........663 22.3.20 DMA burst mode .
Page 22 Contents RM0444 22.4.30 TIM4 timer input selection register (TIM4_TISEL) ....697 22.4.31 TIMx register map ........699 Basic timers (TIM6/TIM7) .
Page 23 RM0444 Contents 24.3.9 One-pulse mode ......... 728 24.3.10 UIF bit remapping .
Page 24 Contents RM0444 25.4.14 Bidirectional break inputs ........769 25.4.15 One-pulse mode .
Page 25 RM0444 Contents 25.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) ....808 25.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) ..809 25.6.4 TIMx status register (TIMx_SR)(x = 16 to 17) .
Page 26 Contents RM0444 26.4.10 Waveform generation ........839 26.4.11 Register update .
Page 27 RM0444 Contents 28.4.4 IWDG status register (IWDG_SR) ......864 28.4.5 IWDG window register (IWDG_WINR) ......865 28.4.6 IWDG register map .
Page 28 Contents RM0444 30.3.13 RTC smooth digital calibration ....... 885 30.3.14 Timestamp function ........887 30.3.15 Calibration clock output .
Page 29 RM0444 Contents 31.3.4 Tamper detection ......... 915 31.4 TAMP low-power modes .
Page 30 Contents RM0444 32.4.18 DMA requests ......... . . 978 32.4.19 Debug mode .
Page 31 RM0444 Contents 33.5.13 USART LIN (local interconnection network) mode ....1026 33.5.14 USART synchronous mode ....... . 1028 33.5.15 USART single-wire Half-duplex communication .
Page 32 Contents RM0444 34.4.3 LPUART character description ......1090 34.4.4 LPUART FIFOs and thresholds ......1091 34.4.5 LPUART transmitter .
Page 33 RM0444 Contents 35.5.2 Communications between one master and one slave ... . 1142 35.5.3 Standard multi-slave communication ......1144 35.5.4 Multi-master communication .
Page 34 Contents RM0444 FD controller area network (FDCAN) ......1196 36.1 Introduction ..........1196 36.2 FDCAN main features .
Page 35 RM0444 Contents 36.4.23 CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) ..1249 36.4.24 FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) ... . 1249 36.4.25 FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) .
Page 36 Contents RM0444 37.6.3 USB register map ........1306 USB Type-C™...
Page 37 RM0444 Contents 38.7.15 UCPD Rx ordered set extension register 2 (UCPD_RX_ORDEXTR2) ....... . . 1344 38.7.16 UCPD register map .
Page 38 Contents RM0444 40.3.2 SW-DP pin assignment ........1366 40.3.3 Internal pull-up &...
Page 39 RM0444 List of tables List of tables Table 1. Peripherals versus products ..........54 Table 2.
Page 40 List of tables RM0444 Table 52. DMAMUX: assignment of multiplexer inputs to resources ......300 Table 53. DMAMUX: assignment of trigger inputs to resources .
Page 41 RM0444 List of tables Table 104. GCM last block definition ..........493 Table 105.
Page 42 List of tables RM0444 Table 154. RTC register map and reset values ......... 910 Table 155.
Page 43 RM0444 List of tables Table 205. Rx FIFO element ............1220 Table 206.
Page 44 List of figures RM0444 List of figures Figure 1. System architecture ............56 Figure 2.
Page 45 RM0444 List of figures Figure 49. Analog watchdog guarded area ..........369 Figure 50.
Page 46 List of figures RM0444 Figure 101. Advanced-control timer block diagram ........525 Figure 102.
Page 47 RM0444 List of figures Figure 153. Example of counter operation in encoder interface mode......573 Figure 154. Example of encoder interface mode with TI1FP1 polarity inverted....574 Figure 155.
Page 48 List of figures RM0444 Figure 204. Master/Slave timer example ..........663 Figure 205.
Page 49 RM0444 List of figures Figure 250. Capture/compare channel (example: channel 1 input stage) ..... . 755 Figure 251. Capture/compare channel 1 main circuit ........755 Figure 252.
Page 50 List of figures RM0444 Figure 299. 10-bit address read access with HEAD10R=0 ....... . . 952 Figure 300.
Page 51 RM0444 List of figures Figure 347. Mute mode using address mark detection ........1103 Figure 348.
Page 52 List of figures RM0444 Figure 396. Pin control in Bus Monitoring mode ........1207 Figure 397.
Page 53: Documentation Conventions
RM0444 Documentation conventions Documentation conventions General information ® ®(a) The STM32G0x1 devices have an Arm Cortex -M0+ core. List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit.
Page 54: Glossary
Documentation conventions RM0444 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • SWD-DP (SWD DEBUG PORT): SWD-DP provides a 2-pin (clock and data) interface ®...
Page 55 RM0444 Documentation conventions Table 1. Peripherals versus products (continued) STM32G0 STM32G0 STM32G0 STM32G0 STM32G0 STM32G0 STM32G0 STM32G0 Feature I2C2 independent clock sel. SPI3 I2S2 USART3, USART4 USART5, USART6 USART2 independent clock sel. USART3 independent clock sel. LPUART2 UCPD1, UCPD2 FDCAN1, FDCAN2 DMA2 MCO2...
Page 56: Memory And Bus Architecture
Memory and bus architecture RM0444 Memory and bus architecture System architecture The main system consists of: • Two masters: ® – Cortex -M0+ core – General-purpose DMA • Three slaves: – Internal SRAM – Internal Flash memory – AHB with AHB-to-APB bridge that connects all the APB peripherals These are interconnected using a multilayer AHB bus architecture as shown in Figure Figure 1.
Page 57 RM0444 Memory and bus architecture Bus matrix The bus matrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. The bus matrix is composed of masters (CPU, DMA) and slaves (Flash memory interface, SRAM and AHB-to-APB bridge). AHB peripherals are connected on system bus through the bus matrix to allow DMA access.
Page 58: Memory Organization
RM0444 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 59: Memory Map And Register Boundary Addresses
RM0444 2.2.2 Memory map and register boundary addresses Figure 2. Memory map Used space Reserved space 0 x 5 0 0 0 1FFF 0xFFFF FFFF IOPORT 0 x 5 0 0 0 0 0 0 0 block 7 Arm Cortex M0+ internal peripherals 0 x E 0 0 0 0 0 0 0 0 x 4 0 0 2 63FF...
Page 60: Table 2. Stm32G0B1Xx And Stm32G0C1Xx Memory Boundary Addresses
RM0444 Table 2. STM32G0B1xx and STM32G0C1xx memory boundary addresses Type Boundary address Size Memory Area Register description 0x2002 4000 - 0x3FFF FFFF ~512 MB Reserved SRAM 0x2000 0000 - 0x2002 3FFF 144 KB SRAM Section 2.3 on page 65 0x1FFF 7880- 0x1FFF FFFF ~34 KB Reserved 0x1FFF 7800 - 0x1FFF 787F...
Page 61: Table 5. Stm32G031Xx And Stm32G041Xx Memory Boundary Addresses
RM0444 Table 4. STM32G051xx and STM32G061xx memory boundary addresses (continued) Type Boundary address Size Memory Area Register description 0x1FFF 7880- 0x1FFF FFFF ~34 KB Reserved 0x1FFF 7800 - 0x1FFF 787F 128 B Option bytes Section 3.4 on page 81 0x1FFF 7500 - 0x1FFF 77FF 768 B Engineering bytes 0x1FFF 7400- 0x1FFF 74FF...
Page 62: Table 6. Stm32G0X1 Peripheral Register Boundary Addresses
RM0444 The following table gives the boundary addresses of the peripherals. Table 6. STM32G0x1 peripheral register boundary addresses Boundary address Size Peripheral Peripheral register map ® Cortex -M0+ internal 0xE000 0000 - 0xE00F FFFF 1MB peripherals 0x5000 1800 - 0x5FFF FFFF ~256 MB Reserved 0x5000 1400 - 0x5000 17FF...
Page 63 RM0444 Table 6. STM32G0x1 peripheral register boundary addresses (continued) Boundary address Size Peripheral Peripheral register map 0x4001 4000 - 0x4001 43FF 1 KB TIM15 Section 25.6.21 on page 830 0x4001 3C00 - 0x4001 3FFF 1 KB USART6 Section 33.8.15 on page 1086 0x4001 3800 - 0x4001 3BFF 1 KB USART1...
Page 64: Embedded Sram
RM0444 Table 6. STM32G0x1 peripheral register boundary addresses (continued) Boundary address Size Peripheral Peripheral register map 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 Section 32.7.12 on page 998 0x4000 5400 - 0x4000 57FF 1 KB I2C1 Section 32.7.12 on page 998 0x4000 5000 - 0x4000 53FF 1 KB USART5...
Page 65: Flash Memory Overview
RM0444 The SRAM can be accessed by bytes, half-words (16 bits) or full words (32 bits), at maximum system clock frequency without wait state and thus by both CPU and DMA. Parity check The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user option byte (refer to Section 3.4: FLASH option bytes).
Page 66 RM0444 Table 8. Boot modes (continued) Boot mode configuration Selected boot area BOOT_ nBOOT1 BOOT0 nBOOT_SEL nBOOT0 LOCK bit Embedded SRAM Main Flash memory System memory Embedded SRAM Main Flash memory forced The boot mode configuration is latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set boot mode configuration related to the required boot mode.
Page 67 This modification is performed by programming the MEM_MODE bits in SYSCFG configuration register 1 (SYSCFG_CFGR1). Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces: •...
Page 68: Embedded Flash Memory (Flash)
Embedded Flash memory (FLASH) RM0444 Embedded Flash memory (FLASH) FLASH Introduction ® The Flash memory interface manages CPU (Cortex -M0+) AHB to the Flash memory. It implements erase and program Flash memory operations, read and write protection, and security mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 69: Flash Functional Description
(DFU) and FDCAN2 (applies to STM32G0B1xx and STM32G0C1xx). On the manufacturing line, the devices are programmed and protected against spurious write/erase operations. For further details, refer to the AN2606 available from www.st.com. – 1 Kbyte (128 double words) OTP (one-time programmable) for user data. The OTP data cannot be erased and can be written only once.
Page 70: Table 10. Flash Memory Organization For 256 Kbytes Dual-Bank Devices
Embedded Flash memory (FLASH) RM0444 Table 9. Flash memory organization for single-bank devices (continued) Size 16 Kbyte 32 Kbyte 64 Kbyte 128 Kbyte Area Addresses (bytes) devices devices devices devices 0x0801 F800 - 0x0801 FFFF Page 63 0x0801 0000 - 0x0801 07FF Page 32 0x0800 F800 - 0x0800 FFFF Page 31...
Page 71: Flash Empty Check
RM0444 Embedded Flash memory (FLASH) Table 11. Flash memory organization for 512 Kbytes dual-bank devices Memory Area Addresses Size (bytes) type Bank 1 0x1FFF 7800 - 0x1FFF 787F Option bytes Information Bank 1 0x1FFF 7000 - 0x1FFF 73FF OTP area block Bank 1 0x1FFF 0000 - 0x1FFF 6FFF...
Page 72: Flash Read Access Latency
Embedded Flash memory (FLASH) RM0444 Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected, but two errors detection is not supported. When an ECC error is reported, a new read at the failing address may not generate an ECC error if the data is still present in the current buffer, even if ECCC and ECCD are cleared.
Page 73: Flash Memory Acceleration
RM0444 Embedded Flash memory (FLASH) Decreasing the CPU frequency Modify the system clock source by writing the SW bits of the RCC_CFGR register. If needed, modify the core clock prescaler by writing the HPRE bits of RCC_CFGR. Check that the new system clock source or/and the new core clock prescaler value is/are taken into account by reading the clock source status (SWS bits) of the RCC_CFGR register, or/and the AHB prescaler value (HPREF bit), of the RCC_CFGR register, and wait until the programmed new system clock source or/and new Flash...
Page 74: Flash Program And Erase Operations
Embedded Flash memory (FLASH) RM0444 3.3.6 FLASH program and erase operations The device-embedded Flash memory can be programmed using in-circuit programming or in-application programming. The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory, using SWD protocol or the supported interfaces by the system boot loader, to load the user application for the CPU, into the microcontroller.
Page 75: Table 13. Page Erase Overview
RM0444 Embedded Flash memory (FLASH) Table 13. Page erase overview SEC_PROT PCROP WRP PCROP_RDP Comment WRPERR CPU bus error Page is erased Page erase aborted (no page erase started) Protected pages only To erase a page (2 Kbytes), follow the procedure below: Check that no Flash memory operation is ongoing by checking the BSY1 bit of the FLASH status register (FLASH_SR).
Page 76: Flash Main Memory Programming Sequences
Embedded Flash memory (FLASH) RM0444 Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. 3.3.8 FLASH Main memory programming sequences The Flash memory is programmed 72 bits (64-bit data plus 8-bit ECC) at a time.
Page 77 RM0444 Embedded Flash memory (FLASH) The Main Flash memory programming sequence in standard mode is described below: Perform a mass or page erase. If not, PGSERR is set. Check that no Main Flash memory operation is ongoing by checking the BSY1 bit of the FLASH status register (FLASH_SR)..
Page 78 Embedded Flash memory (FLASH) RM0444 – In fast programming: the data to program doesn’t belong to the same row than the previous programmed double words, or the address to program is not greater than the previous one. • PGSERR: Programming Sequence Error PGSERR is set if one of the following conditions occurs: –...
Page 79: Read-While-Write (Rww) Function
RM0444 Embedded Flash memory (FLASH) Programming and cache If an erase operation in Flash memory also concerns data in the instruction cache, the user has to ensure that these data are rewritten before they are accessed during code execution. Note: The cache should be flushed only when it is disabled (ICEN = 0).
Page 80: Flash Option Bytes
Embedded Flash memory (FLASH) RM0444 The word write operation is completed when the corresponding busy flag (BSY1 or BSY2) is back to low. The EOP interrupt can be used to indicate that event to the application software. FLASH option bytes 3.4.1 FLASH option byte description The option bytes are configured by the end user depending on the application requirements.
Page 81: Table 16. Organization Of Option Bytes
SEC_SIZE 1. The upper 32-bits of the double-word address contain the inverted data from the lower 32 bits. User and read protection option bytes Flash memory address: 0x1FFF 7800 Reset value: 0xFFFF FEAA (ST production value) RAM_ IWGD NRST_MODE nBOOT...
Page 82 Embedded Flash memory (FLASH) RM0444 Bits 31:30 Reserved, must be kept at reset value. Bit 29 IRHEN: Internal reset holder enable bit 0: Internal resets are propagated as simple pulse on NRST pin 1: Internal resets drives NRST pin low until it is seen as low level Bits 28: 27 NRST_MODE[1:0] 00: Reserved 01: Reset Input only: a low level on the NRST pin generates system reset, internal RESET...
Page 83 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active PCROP1A start address option bytes Flash memory address: 0x1FFF 7808 Reset value: 0xFFFF FFFF (ST production value) Res. Res. Res. Res.
Page 84 Embedded Flash memory (FLASH) RM0444 PCROP1A end address option bytes Flash memory address: 0x1FFF 7810 Reset value: 0x0000 0000 (ST production value) PCROP_RDP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 85 RM0444 Embedded Flash memory (FLASH) WRP1B address option bytes Flash memory address: 0x1FFF 7820 Reset value: 0x0000 00FF (ST production value) Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_END[6:0] Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 86 Note: Values corresponding to addresses outside the Main memory are not allowed. PCROP2A start address option bytes Flash memory address: 0x1FFF 7838 Reset value: 0xFFFF FFFF (ST production value) The register pertains to dual-bank devices only. In single-bank devices, it is reserved. Res.
Page 87 PCROP2A_END contains the offset of the last PCROP subpage of the PCROP2A area in Bank 2 of dual-bank devices. Note: Values corresponding to addresses outside the Main memory are not allowed. WRP2A address option bytes Flash memory address: 0x1FFF 7848 Reset value: 0x0000 00FF (ST production value) Res. Res. Res. Res.
Page 88 Note: Values corresponding to addresses outside the Main memory are not allowed. PCROP2B start address option bytes Flash memory address: 0x1FFF 7858 Reset value: 0xFFFF FFFF (ST production value) The register pertains to dual-bank devices only. In single-bank devices, it is reserved. Res.
Page 89: Flash Option Byte Programming
PCROP2B_END contains the offset of the last PCROP subpage of the PCROP2B area in Bank 2 of dual-bank devices. Note: Values corresponding to addresses outside the Main memory are not allowed. Security option bytes Flash memory address: 0x1FFF 7870 Reset value: 0x0000 0000 (ST production value) Res. Res. Res. Res.
Page 90 Embedded Flash memory (FLASH) RM0444 Any wrong sequence locks up the Flash memory option registers until the next system reset. In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is generated. The user options can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.
Page 91: Flash Memory Protection
RM0444 Embedded Flash memory (FLASH) If the word and its complement are matching, the option word/byte is copied into the option register. If the comparison between the word and its complement fails, a status bit OPTVERR is set. Mismatch values are forced into the option registers: –...
Page 92: Table 17. Flash Memory Read Protection Status
Embedded Flash memory (FLASH) RM0444 Table 17. Flash memory read protection status RDP byte value RDP complement byte value Read protection level 0xAA 0x55 Level 0 Any values except the combinations [0xAA, 0x55] and [0xCC, 0x33] Level 1 (default) 0xCC 0x33 Level 2 The System memory area is read-accessible whatever the protection level.
Page 93 RM0444 Embedded Flash memory (FLASH) Once in Level 2, it is no more possible to modify the read protection level. With the PCROP_RDP bit of the FLASH PCROP area A end address register (FLASH_PCROP1AER) set, the change from Level 1 to Level 0 triggers full mass erase of the Main Flash memory.
Page 94: Flash Proprietary Code Readout Protection (Pcrop)
Embedded Flash memory (FLASH) RM0444 Figure 3. Changing read protection (RDP) level Level 1 RDP ≠ 0xAA ≠ 0xCC RDP = 0xAA RDP = 0xCC RDP ≠ 0xCC ≠ 0xAA Level 2 Level 0 RDP = 0xCC RDP = 0xAA RDP = 0xCC Read-protection level increase Read-protection level decrease (with full or partial mass erase)
Page 95 RM0444 Embedded Flash memory (FLASH) The protected area is execute-only: it can only be reached by the STM32 CPU, with an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. The PCROP areas have subpage (512-byte) granularity. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0 (refer to Changing the read...
Page 96: Flash Write Protection (Wrp)
Embedded Flash memory (FLASH) RM0444 Table 20: PCROP protection PCROP register values PCROP-protected area (x = A or B, y = 1 or 2) PCROPyx_STRT = PCROPyx_END Full Flash memory PCROPyx_STRT > PCROPyx_END None (unprotected) Subpages from PCROPyx_STRT to PCROPyx_END PCROPyx_STRT <...
Page 97: Securable Memory Area
RM0444 Embedded Flash memory (FLASH) If an erase/program operation to a write-protected part of the Flash memory is attempted, the write protection error flag (WRPERR) of the FLASH_SR register is set. This flag is also set for any write access to: –...
Page 98: Disabling Core Debug Access
Embedded Flash memory (FLASH) RM0444 Table 22. Securable memory erase at RDP Level 1 to Level 0 change Securable memory size PCROP_RDP Erased pages (SEC_SIZEx[7:0]) All (mass erase) All but PCROP > 0 All (mass erase) All but PCROP outside the >...
Page 99: Table 23. Flash Interrupt Requests
RM0444 Embedded Flash memory (FLASH) Table 23. FLASH interrupt requests Event flag/interrupt Interrupt enable Interrupt event Event flag clearing method control bit End of operation Write EOP=1 EOPIE Operation error OPERR Write OPERR=1 ERRIE Read protection error RDERR Write RDERR=1 RDERRIE Write protection error WRPERR...
Page 100: Flash Registers
Embedded Flash memory (FLASH) RM0444 FLASH registers 3.7.1 FLASH access control register (FLASH_ACR) Address offset: 0x000 Reset value: 0x0004 0600 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EMPTY _SWEN Res. Res. Res. Res. ICRST Res.
Page 101: Flash Key Register (Flash_Keyr)
RM0444 Embedded Flash memory (FLASH) Bit 8 PRFTEN: CPU Prefetch enable 0: CPU Prefetch disabled 1: CPU Prefetch enabled Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 LATENCY[2:0]: Flash memory access latency The value in this bitfield represents the ratio of the HCLK clock period to the Flash memory access time.
Page 102: Flash Status Register (Flash_Sr)
Embedded Flash memory (FLASH) RM0444 3.7.4 FLASH status register (FLASH_SR) Address offset: 0x010 Reset value: 0x000X 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CFGBSY BSY2 BSY1 OPTV FAST MISS PROG Res. Res. Res. Res.
Page 103 RM0444 Embedded Flash memory (FLASH) Bit 8 MISSERR: Fast programming data miss error In Fast programming mode, 32 double words (256 bytes) must be sent to Flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed.
Page 104: Flash Control Register (Flash_Cr)
Embedded Flash memory (FLASH) RM0444 3.7.5 FLASH control register (FLASH_CR) Address offset: 0x014 Reset value: 0xC000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access This register cannot be modified when CFGBSY in FLASH status register (FLASH_SR) set.
Page 105 RM0444 Embedded Flash memory (FLASH) Bit 25 ERRIE: Error interrupt enable This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register. 0: Disable 1: Enable Bit 24 EOPIE: End-of-operation interrupt enable This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register. 0: Disable 1: Enable Bits 23:19 Reserved, must be kept at reset value.
Page 106: Flash Ecc Register (Flash_Eccr)
Embedded Flash memory (FLASH) RM0444 3.7.6 FLASH ECC register (FLASH_ECCR) Address offset: 0x018 Reset value: 0x0000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access This register applies to single-bank products and to Bank 1 of dual-bank products. SYSF_ ECCD ECCC...
Page 107: Flash Ecc Register 2 (Flash_Eccr2)
RM0444 Embedded Flash memory (FLASH) 3.7.7 FLASH ECC register 2 (FLASH_ECCR2) Address offset: 0x01C Reset value: 0x0000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access This register applies to Bank 2 of dual-bank products. SYSF_ ECCD ECCC...
Page 108: Flash Option Register (Flash_Optr)
Embedded Flash memory (FLASH) RM0444 3.7.8 FLASH option register (FLASH_OPTR) Address offset: 0x020 Reset value: 0b11XX XXXX 1X1X XXXX XXXX XXXX XXXX XXXX (The option bits are loaded with values from Flash memory at power-on reset release.) Access: no wait state when no Flash memory operation is on going, word, half-word and byte access IWGD NRST_MODE...
Page 109 RM0444 Embedded Flash memory (FLASH) Bit 20 nSWAP_BANK: Empty check boot configuration This bit selects the bank that is the subject of empty check upon boot. 0: Bank 1 1: Bank 2 The bit is ignored when the BOOT_LOCK bit is set. Bit 19 WWDG_SW: Window watchdog selection 0: Hardware window watchdog 1: Software window watchdog...
Page 110: Flash Pcrop Area A Start Address Register (Flash_Pcrop1Asr)
Embedded Flash memory (FLASH) RM0444 3.7.9 FLASH PCROP area A start address register (FLASH_PCROP1ASR) Address offset: 0x024 Reset value: 0b0000 0000 0000 0000 0000 000X XXXX XXXX (The option bits are loaded with values from Flash memory at power-on reset release.) Access: no wait state when no Flash memory operation is on going, word, half-word access This register applies to single-bank devices and to Bank 1 of dual-bank devices.
Page 111: Flash Wrp Area A Address Register (Flash_Wrp1Ar)
RM0444 Embedded Flash memory (FLASH) Bit 31 PCROP_RDP: PCROP area erase upon RDP level regression This bit determines whether the PCROP area (and the totality of the PCROP area boundary pages) is erased by the mass erase triggered by the RDP level regression from Level 1 to Level 0: 0: Not erased 1: Erased...
Page 112: Flash Wrp Area B Address Register (Flash_Wrp1Br)
Embedded Flash memory (FLASH) RM0444 3.7.12 FLASH WRP area B address register (FLASH_WRP1BR) Address offset: 0x030 Reset value: 0b0000 0000 0XXX XXXX 0000 0000 0XXX XXXX (The option bits are loaded with values from Flash memory at power-on reset release.) Access: no wait state when no Flash memory operation is on going, word, half-word and byte access.
Page 113: Flash Pcrop Area B End Address Register (Flash_Pcrop1Ber)
RM0444 Embedded Flash memory (FLASH) 3.7.14 FLASH PCROP area B end address register (FLASH_PCROP1BER) Address offset: 0x038 Reset value: ‘b0000 0000 0000 0000 0000 000X XXXX XXXX (The option bits are loaded with values from Flash memory at power-on reset release.) Access: no wait state when no Flash memory operation is on going, word, half-word access Res.
Page 114: Flash Pcrop2 Area A End Address Register (Flash_Pcrop2Aer)
Embedded Flash memory (FLASH) RM0444 3.7.16 FLASH PCROP2 area A end address register (FLASH_PCROP2AER) Address offset: 0x048 Reset value: 0bX000 0000 0000 0000 0000 000X XXXX XXXX (The option bits are loaded with values from Flash memory at power-on reset release.) Access: no wait state when no Flash memory operation is on going, word, half-word access.
Page 115: Flash Wrp2 Area B Address Register (Flash_Wrp2Br)
RM0444 Embedded Flash memory (FLASH) 3.7.18 FLASH WRP2 area B address register (FLASH_WRP2BR) Address offset: 0x050 Reset value: 0b0000 0000 0XXX XXXX 0000 0000 0XXX XXXX (The option bits are loaded with values from Flash memory at power-on reset release.) Access: no wait state when no Flash memory operation is on going, word, half-word and byte access.
Page 116: Flash Pcrop2 Area B End Address Register (Flash_Pcrop2Ber)
Embedded Flash memory (FLASH) RM0444 3.7.20 FLASH PCROP2 area B end address register (FLASH_PCROP2BER) Address offset: 0x058 Reset value: ‘b0000 0000 0000 0000 0000 000X XXXX XXXX (The option bits are loaded with values from Flash memory at power-on reset release.) Access: no wait state when no Flash memory operation is on going, word, half-word access Res.
Page 117: Flash Register Map
RM0444 Embedded Flash memory (FLASH) 3.7.22 FLASH register map Table 24. FLASH register map and reset values Offset Register LATENCY FLASH_ACR [2:0] 0x000 Reset value Reserved 0x004 Reset value FLASH_KEYR KEYR[31:0] 0x008 Reset value FLASH_OPT OPTKEY[31:0] KEYR 0x00C Reset value FLASH_SR 0x010 Reset value...
Page 118 Embedded Flash memory (FLASH) RM0444 Table 24. FLASH register map and reset values (continued) Offset Register FLASH_ PCROP1B_END[8:0] PCROP1BER 0x038 Reset value X X X X X X X X X 0x03C - Reserved 0x043 FLASH_ PCROP2A_STRT[8:0] PCROP2ASR 0x044 Reset value X X X X X X X X X FLASH_ PCROP2A_END[8:0]...
Page 119: Power Control (Pwr)
RM0444 Power control (PWR) Power control (PWR) Power supplies The STM32G0x1 devices require a 1.7 V to 3.6 V operating supply voltage (V ). Several different power supplies are provided to specific peripherals: • = 1.7 V (1.60 V) to 3.6 V is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks.
Page 120: Adc And Dac Reference Voltage
Power control (PWR) RM0444 Figure 5. Power supply overview domain REF+ VREF+ A/D converter Comparators D/A converter Voltage reference buffer DDIO1 domain I/O ring DDIO1 DDIO2 domain VDDIO2 I/O ring DDIO2 domain Reset block domain Temp. sensor CORE PLL, HSI Core Standby circuitry VSS/VSSA...
Page 121 RM0444 Power control (PWR) Warning: During (temporization at V startup) or after a PDR RSTTEMPO has been detected, the power switch between V and V remains connected to V During the startup phase, if V is established in less than (refer to the datasheet for the value of t RSTTEMPO RSTTEMPO...
Page 122: Voltage Regulator
Power control (PWR) RM0444 VBAT battery charging When V is present, it is possible to charge the external battery on VBAT through an internal resistance. The VBAT charging is done either through a 5 kΩ resistor or through a 1.55 kΩ resistor depending on the VBRS bit value in the PWR_CR4 register.
Page 123: Dynamic Voltage Scaling Management
RM0444 Power control (PWR) 4.1.4 Dynamic voltage scaling management The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals (V ), according to CORE the application performance and power consumption needs. Dynamic voltage scaling to increase V is known as overvolting.
Page 124: Power Supply Supervisor
Power control (PWR) RM0444 Power supply supervisor 4.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) The device features an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out reset (BOR) circuitry. The POR/PDR is active in all power modes. The BOR can be enabled or disabled only through option bytes.
Page 125: Programmable Voltage Detector (Pvd)
RM0444 Power control (PWR) For more details on the brown-out reset thresholds, refer to the electrical characteristics section in the datasheet. 4.2.2 Programmable voltage detector (PVD) The PVD can be used to monitor the V power supply by comparing it to the thresholds selected through PVDRT[2:0] bits (rising thresholds) and PVDFT[2:0] bits (falling thresholds) in the Power control register 2...
Page 126: Low-Power Modes
Power control (PWR) RM0444 Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several low- power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 127: Figure 8. Low-Power Modes State Diagram
RM0444 Power control (PWR) behavior is not guaranteed in case of a power voltage drop. Refer to Section 4.3.9: Shutdown mode. In addition, the power consumption in Run mode can be reduced by one of the following means: • Slowing down the system clocks •...
Page 128: Table 25. Low-Power Mode Summary
Power control (PWR) RM0444 Table 25. Low-power mode summary Voltage Wakeup Wakeup regulators Mode name Entry Effect on clocks source system clock WFI or Return Sleep CPU clock OFF Same as before Any interrupt from ISR entering Sleep (Sleep-now or no effect on other clocks mode Sleep-on-exit)
Page 129: Table 26. Functionalities Depending On The Working Mode
RM0444 Power control (PWR) Table 26. Functionalities depending on the working mode Stop 0/1 Standby Shutdown Function Sleep VBAT Flash memory SRAM Backup Registers DMA1/2 HSI16 HSI48 CSS on LSE RTC / Auto wakeup TAMP1/2/3 USART1/2 USART3/4/5/6 LPUART1/2 I2C1 I2C2/3 SPI1/2/3 VREFBUF COMP1/2/3...
Page 130 Power control (PWR) RM0444 Table 26. Functionalities depending on the working mode (continued) Stop 0/1 Standby Shutdown Function Sleep VBAT Temperature sensor TIMx LPTIM1/2 IWDG WWDG SysTick timer FDCAN1/2 up to up to (10) (12) GPIOs pins pins (11) (11) 1.
Page 131: Run Mode
RM0444 Power control (PWR) Debug mode By default, the debug connection is lost if the user application puts the MCU in Stop 0, Stop1, Shutdown, or Standby mode while the debug features are used. This is due to the ® fact that the Cortex -M0+ core is no longer clocked.
Page 132: Low-Power Modes
Power control (PWR) RM0444 Exiting Low-power run mode To exit Low-power run mode, proceed as follows: Force the regulator in main mode by clearing the LPR bit in the Power control register 1 (PWR_CR1). Wait until REGLPF bit is cleared in the Power status register 2 (PWR_SR2).
Page 133: Sleep Mode
RM0444 Power control (PWR) ® When SEVONPEND = 1 in the Cortex -M0+ system control register: by enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
Page 134: Low-Power Sleep Mode (Lp Sleep)
Power control (PWR) RM0444 Table 28. Sleep mode summary (continued) Characteristic Description If WFI or return from ISR was used for entry Interrupt: refer to Table 58: Vector table If WFE was used for entry and SEVONPEND = 0: Mode exit Wakeup event: refer to Section 13.3.2: EXTI direct event input wakeup If WFE was used for entry and SEVONPEND = 1:...
Page 135: Stop 0 Mode
RM0444 Power control (PWR) Table 29. Low-power sleep mode summary Characteristic Description Low-power sleep mode is entered from the Low-power run mode. WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 – No interrupt (for WFI) or event (for WFE) is pending ®...
Page 136 Power control (PWR) RM0444 Entering Stop 0 mode The MCU enters Stop 0 mode according to section Entering low-power modes, when the ® SLEEPDEEP bit in the Cortex -M0+ System Control register is set. Refer to Table 30: Stop 0 mode summary for details on how to enter Stop 0 mode.
Page 137: Table 30. Stop 0 Mode Summary
RM0444 Power control (PWR) Table 30. Stop 0 mode summary Characteristic Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP bit is set in Cortex -M0+ System Control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 138: Stop 1 Mode
Power control (PWR) RM0444 4.3.7 Stop 1 mode The Stop 1 mode is the same as Stop 0 mode except that the main regulator is off, and only the low-power regulator is on. Stop 1 mode can be entered from Run mode and from Low- power run mode.
Page 139: Standby Mode
RM0444 Power control (PWR) 4.3.8 Standby mode The Standby mode allows to achieve the lowest power consumption with BOR. It is based ® on the Cortex -M0+ deepsleep mode, with the voltage regulators disabled (except when the SRAM content is preserved). The PLL, the HSI16 and the HSE oscillators are also switched off.
Page 140: Table 32. Standby Mode Summary
Power control (PWR) RM0444 Exiting Standby mode The MCU exits Standby mode according to section Entering low-power modes. The SBF status flag in the Power control register 3 (PWR_CR3) indicates that the MCU was in Standby mode. All registers are reset after wakeup from Standby except for Power control register 3 (PWR_CR3).
Page 141: Shutdown Mode
RM0444 Power control (PWR) 4.3.9 Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. It is based on the deepsleep mode, with the voltage regulator disabled. The V domain is consequently CORE powered off. The PLL, the HSI16, the LSI and the HSE oscillators are also switched off. SRAM and register contents are lost except for registers in the RTC domain.
Page 142: Auto-Wakeup From Low-Power Mode
Power control (PWR) RM0444 Exiting Shutdown mode The MCU exits Shutdown mode according to section Exiting low-power modes. A power-on reset occurs when exiting from Shutdown mode. All registers (except for the ones in the RTC domain) are reset after wakeup from Shutdown. Refer to Table 33: Shutdown mode summary for more details on how to exit Shutdown...
Page 143: Pwr Registers
RM0444 Power control (PWR) PWR registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 4.4.1 Power control register 1 (PWR_CR1) Address offset: 0x00 Reset value: 0x0000 0208. This register is reset after wakeup from Standby mode. Res.
Page 144: Power Control Register 2 (Pwr_Cr2)
Power control (PWR) RM0444 Bit 4 FPD_LPRUN: Flash memory powered down during Low-power run mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Low-power run mode. The Flash memory can be put in power- down mode only when the user code is executed from SRAM.
Page 145 RM0444 Power control (PWR) Bit 8 PVMENUSB: USB supply voltage monitoring enable This bit enables the monitoring of the USB supply with respect to 1.2 V threshold. 0: Disable 1: Enable Bit 7 PVMENDAC: DAC supply voltage monitoring enable This bit enables the monitoring of the DAC supply with respect to 1.8 V threshold. 0: Disable 1: Enable Bits 6:4 PVDRT[2:0]: Power voltage detector rising threshold selection.
Page 146: Power Control Register 3 (Pwr_Cr3)
Power control (PWR) RM0444 4.4.3 Power control register 3 (PWR_CR3) Address offset: 0x08 Reset value: 0x0000 8000. This register is not reset when exiting Standby modes and with the PWRRST bit in the APB peripheral reset register 1 (RCC_APBRSTR1). Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).
Page 147: Power Control Register 4 (Pwr_Cr4)
RM0444 Power control (PWR) Bit 4 EWUP5: Enable WKUP5 wakeup pin When this bit is set, the WKUP5 external wakeup pin is enabled and triggers a wakeup from Standby or Shutdown mode when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register.
Page 148: Power Status Register 1 (Pwr_Sr1)
Power control (PWR) RM0444 Bit 5 WP6: WKUP6 wakeup pin polarity WKUP6 external wakeup signal polarity (level or edge) triggering wakeup event: 0: High level or rising edge 1: Low level or falling edge Bit 4 WP5: WKUP5 wakeup pin polarity WKUP5 external wakeup signal polarity (level or edge) triggering wakeup event: 0: High level or rising edge 1: Low level or falling edge...
Page 149: Power Status Register 2 (Pwr_Sr2)
RM0444 Power control (PWR) Bit 8 SBF: Standby flag This bit is set by hardware when the device enters Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.
Page 150 Power control (PWR) RM0444 Bits 31:16 Reserved, must be kept at reset value. Bit 15 PVMODAC: V monitoring output flag This flag indicates the readiness of the V supply voltage (excess of PVM threshold of about 1.8 V). 0: V not ready 1: V ready...
Page 151: Power Status Clear Register (Pwr_Scr)
RM0444 Power control (PWR) 4.4.7 Power status clear register (PWR_SCR) Address offset: 0x18 Reset value: 0x0000 0000. Access: three additional APB cycles are needed to write this register, compared to a standard APB write. Res. Res. Res. Res. Res. Res. Res.
Page 152: Power Port A Pull-Down Control Register (Pwr_Pdcra)
Power control (PWR) RM0444 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port A pull-up bit y (y = 0 to 15) Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[y] I/O.
Page 153: Power Port B Pull-Down Control Register (Pwr_Pdcrb)
RM0444 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port B pull-up bit y (y = 0 to 15) Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[y] I/O.
Page 154: Power Port C Pull-Down Control Register (Pwr_Pdcrc)
Power control (PWR) RM0444 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port C pull-up bit y (y = 0 to 15) Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[y] I/O.
Page 155: Power Port D Pull-Down Control Register (Pwr_Pdcrd)
RM0444 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port D pull-up bit y (y = 0 to 15) Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[y] I/O.
Page 156: Power Port E Pull-Down Control Register (Pwr_Pdcre)
Power control (PWR) RM0444 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port E pull-up bit y (y = 0 to 15) Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PE[y] I/O.
Page 157: Power Port F Pull-Down Control Register (Pwr_Pdcrf)
RM0444 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU13 PU12 PU11 PU10 Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 PUy: Port F pull-up bit y (y = 0 to 13) Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[y] I/O.
Page 158: Pwr Register Map
Power control (PWR) RM0444 4.4.20 PWR register map Table 34. PWR register map and reset values Offset Register LPMS PWR_CR1 [1:0] [2:0] 0x000 Reset value PVDRT PVDFT PWR_CR2 [2:0] [2:0] 0x004 Reset value PWR_CR3 0x008 Reset value PWR_CR4 0x00C Reset value PWR_SR1 0x010 Reset value...
Page 159 RM0444 Power control (PWR) Table 34. PWR register map and reset values (continued) Offset Register PWR_PUCRD 0x038 Reset value PWR_PDCRD 0x03C Reset value PWR_PUCRE 0x040 Reset value PWR_PDCRE 0x044 Reset value PWR_PUCRF 0x048 Reset value PWR_PDCRF 0x04C Reset value Refer to Section 2.2 on page 58 for the register boundary addresses.
Page 160: Reset And Clock Control (Rcc)
Reset and clock control (RCC) RM0444 Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and RTC domain reset. 5.1.1 Power reset A power reset is generated when one of the following events occurs: •...
Page 161: Figure 9. Simplified Diagram Of The Reset Circuit
RM0444 Reset and clock control (RCC) detection of internal reset sources by external components when the line faces a significant capacitive load. • Reset input In this mode, any valid reset signal on the NRST pin is propagated to device internal logic, but resets generated internally by the device are not visible on the pin.
Page 162: Rtc Domain Reset
Reset and clock control (RCC) RM0444 Low-power mode security reset To prevent that critical applications mistakenly enter a low-power mode, three low-power mode security resets are available. If enabled in option bytes, the resets are generated in the following conditions: •...
Page 163: Clocks
RM0444 Reset and clock control (RCC) Clocks The device provides the following clock sources producing primary clocks: • HSI16 RC - a high-speed fully-integrated RC oscillator producing HSI16 clock (about 16 MHz) • HSI48 RC - a high-speed fully-integrated RC oscillator producing HSI48 clock for USB (about 48 MHz) •...
Page 164 Reset and clock control (RCC) RM0444 The peripherals are clocked with the clocks from the bus they are attached to (HCLK for AHB, PCLK for APB) except: • TIMx, with these clock sources to select from: – TIMPCLK (selectable for all timers) running at PCLK frequency if the APB prescaler division factor is set to 1, or at twice the PCLK frequency otherwise –...
Page 165 RM0444 Reset and clock control (RCC) • CEC, with these clock sources to select from: – HSI16 clock divided by 488 – • RTC, with these clock sources to select from: – – – HSE clock divided by 32 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE.
Page 166: Figure 10. Clock Tree
Reset and clock control (RCC) RM0444 Figure 10. Clock tree to IWDG LSI RC 32 kHz RTC WAKEUP from RTC RTCCLK LSCO to RTC OSC32_OUT LSE OSC 32.768 kHz to CEC OSC32_IN Clock HSI16 / 488 detector to UCPD1/2 HSI16 to PWR SYSCLK to AHB bus, core, memory and DMA...
Page 167: Hse Clock
RM0444 Reset and clock control (RCC) 5.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
Page 168: Hsi16 Clock
Reset and clock control (RCC) RM0444 External crystal/ceramic resonator (HSE crystal) The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 11. Refer to the electrical characteristics section of the datasheet for more details.
Page 169: Hsi48 Clock
RM0444 Reset and clock control (RCC) For more details on how to measure the HSI16 frequency variation, refer to Section 5.2.16: Internal/external clock measurement with TIM14/TIM16/TIM17. The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI16 RC is stable or not.
Page 170: Lse Clock
Reset and clock control (RCC) RM0444 An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt enable register (RCC_CIER). The enable bit of each PLL output clock (PLLPEN, PLLQEN, and PLLREN) can be modified at any time without stopping the PLL.
Page 171: System Clock (Sysclk) Selection
RM0444 Reset and clock control (RCC) 5.2.7 System clock (SYSCLK) selection One of the following clocks can be selected as system clock (SYSCLK): • • • HSISYS • • PLLRCLK The system clock maximum frequency is 64 MHz. Upon system reset, the HSISYS clock derived from HSI16 oscillator is selected as system clock.
Page 172: Clock Security System For Lse Clock (Lsecss)
Reset and clock control (RCC) RM0444 Note: If the CSS is enabled and the HSE clock fails, the CSSI occurs and an NMI is automatically generated. The NMI is executed infinitely unless the CSS interrupt pending bit is cleared. It is therefore necessary that the NMI ISR clears the CSSI by setting the CSSC bit in the Clock interrupt clear register...
Page 173: Timer Clock
RM0444 Reset and clock control (RCC) The LSE clock is in the RTC domain, whereas the HSE and LSI clocks are not. Consequently: • If LSE is selected as RTC clock: – The RTC continues to work even if the V supply is switched off, provided the supply is maintained.
Page 174: Internal/External Clock Measurement With Tim14/Tim16/Tim17
Reset and clock control (RCC) RM0444 The multiplexers for MCO and MCO2, respectively, are controlled by the MCOSEL[3:0] and MCO2SEL[3:0] bitfields of the Clock configuration register (RCC_CFGR). Their outputs are further divided by a factor set through the MCOPRE[2:0] and MCO2PRE[2:0] bitfields of the Clock configuration register (RCC_CFGR).
Page 175: Figure 13. Frequency Measurement With Tim16 In Capture Mode
RM0444 Reset and clock control (RCC) TIM16 By setting the TI1SEL[3:0] field of the TIM16_TISEL register, the clock selected for the input capture channel1 of TIM16 can be one of: • GPIO (refer to the alternate function mapping in the device datasheets). •...
Page 176: Peripheral Clock Enable Registers
Reset and clock control (RCC) RM0444 Calibration of the HSI16 oscillator For TIM14, TIM15 and TIM17, the primary purpose of connecting the LSE to the channel 1 input capture is to precisely measure HSISYS (derived from HSI16) selected as system clock.
Page 177: Low-Power Modes
RM0444 Reset and clock control (RCC) Low-power modes • AHB and APB peripheral clocks, including DMA clock, can be disabled by software. • Sleep and Low Power Sleep modes stops the CPU clock. The memory interface clocks (Flash memory and SRAM interfaces) can be stopped by software during sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled.
Page 178: Rcc Registers
Reset and clock control (RCC) RM0444 RCC registers Unless otherwise specified, the RCC registers support word, half-word, and byte access, without any wait state. 5.4.1 Clock control register (RCC_CR) Address offset: 0x00 Power-on reset value: 0x0000 0500 Other types of reset: same as power-on reset, except HSEBYP bit that keeps its previous value.
Page 179 RM0444 Reset and clock control (RCC) Bit 18 HSEBYP: HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
Page 180: Internal Clock Source Calibration Register (Rcc_Icscr)
Reset and clock control (RCC) RM0444 Bit 8 HSION: HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock).
Page 181 RM0444 Reset and clock control (RCC) MCOPRE[3:0] MCOSEL[3:0] MCO2PRE[3:0] MCO2SEL[3:0] Res. PPRE[2:0] HPRE[3:0] Res. Res. SWS[2:0] SW[2:0] 1. Only significant on devices integrating the corresponding output, otherwise reserved. Refer to Section 1.4: Availability of peripherals. Bits 31:28 MCOPRE[3:0]: Microcontroller clock output prescaler This bitfield is controlled by software.
Page 182 Reset and clock control (RCC) RM0444 Bits 23:20 MCO2PRE[3:0]: Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: 0000: 1 0001: 2 0010: 4 0111: 128 1000: 256 1001: 512...
Page 183: Pll Configuration Register (Rcc_Pllcfgr)
RM0444 Reset and clock control (RCC) Bits 11:8 HPRE[3:0]: AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 1000: 2 1001: 4 1010: 8 1011: 16 1100: 64 1101: 128 1110: 256...
Page 184 Reset and clock control (RCC) RM0444 where f is the PLL input clock frequency, f is the PLL VCO frequency, and P, Q and PLLIN R are f division factors and f and f the clock frequencies of the PLLPCLK, PLLP PLLQ PLLR...
Page 185 RM0444 Reset and clock control (RCC) Bits 21:17 PLLP[4:0]: PLL VCO division factor P for PLLPCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: 00000: Reserved 00001: 2 11111: 32 The bitfield can be written only when the PLL is disabled.
Page 186: Rcc Clock Recovery Rc Register (Rcc_Crrcr)
Reset and clock control (RCC) RM0444 Bits 1:0 PLLSRC: PLL input clock source This bit is controlled by software to select PLL clock source, as follows: 00: No clock 01: Reserved 10: HSI16 11: HSE The bitfield can be written only when the PLL is disabled. When the PLL is not used, selecting 00 allows saving power.
Page 187: Clock Interrupt Flag Register (Rcc_Cifr)
RM0444 Reset and clock control (RCC) Bits 31:6 Reserved, must be kept at reset value. Bit 5 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock: 0: Disable 1: Enable Bit 4 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization: 0: Disable...
Page 188 Reset and clock control (RCC) RM0444 Bits 31:10 Reserved, must be kept at reset value. Bit 9 LSECSSF: LSE clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit. 0: No clock security interrupt caused by LSE clock failure 1: Clock security interrupt caused by LSE clock failure Bit 8 CSSF: HSE clock security system interrupt flag...
Page 189: Clock Interrupt Clear Register (Rcc_Cicr)
RM0444 Reset and clock control (RCC) 5.4.8 Clock interrupt clear register (RCC_CICR) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSI48 Res. Res. Res. Res. Res.
Page 190: I/O Port Reset Register (Rcc_Ioprstr)
Reset and clock control (RCC) RM0444 5.4.9 I/O port reset register (RCC_IOPRSTR) Address: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GPIOE GPIOF GPIOD GPIOC GPIOB GPIOA Res.
Page 191: Apb Peripheral Reset Register 1 (Rcc_Apbrstr1)
RM0444 Reset and clock control (RCC) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2 FLASH DMA1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability peripherals.
Page 192 Reset and clock control (RCC) RM0444 UCPD DAC1 UCPD1 I2C3 USART4 USART3 CRSR LPTIM1 LPTIM2 I2C2 I2C1 USART2 UART1 FDCA SPI3 USART6 USART5 UART2 TIM7 TIM6 TIM4 SPI2 TIM3 TIM2 Res. Res. Res. Res. 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability peripherals.
Page 193 RM0444 Reset and clock control (RCC) Bit 23 I2C3RST: I2C3 reset Set and cleared by software. 0: No effect 1: Reset I2C3 Bit 22 I2C2RST: I2C2 reset Set and cleared by software. 0: No effect 1: Reset I2C2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software.
Page 194: Apb Peripheral Reset Register 2 (Rcc_Apbrstr2)
Reset and clock control (RCC) RM0444 Bit 12 FDCAN: FDCAN reset Set and cleared by software. 0: No effect 1: Reset FDCAN Bits 11:10 Reserved, must be kept at reset value. Bit 9 USART6RST: USART3 reset Set and cleared by software. 0: No effect 1: Reset USART6 Bit 8 USART5RST: USART3 reset...
Page 195 RM0444 Reset and clock control (RCC) TIM15 TIM17 TIM16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM14 USART1 SPI1 TIM1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability peripherals.
Page 196: I/O Port Clock Enable Register (Rcc_Iopenr)
Reset and clock control (RCC) RM0444 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bits 10:1 Reserved, must be kept at reset value. Bit 0 SYSCFGRST: SYSCFG, COMP and VREFBUF reset Set and cleared by software.
Page 197: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
RM0444 Reset and clock control (RCC) Bit 2 GPIOCEN: I/O port C clock enable This bit is set and cleared by software. 0: Disable 1: Enable Bit 1 GPIOBEN: I/O port B clock enable This bit is set and cleared by software. 0: Disable 1: Enable Bit 0 GPIOAEN: I/O port A clock enable...
Page 198: Apb Peripheral Clock Enable Register 1 (Rcc_Apbenr1)
Reset and clock control (RCC) RM0444 Bit 8 FLASHEN: Flash memory interface clock enable Set and cleared by software. 0: Disable 1: Enable This bit can only be cleared when the Flash memory is in power down mode. Bits 7:2 Reserved, must be kept at reset value. Bit 1 DMA2EN: DMA2 and DMAMUX clock enable Set and cleared by software.
Page 199 RM0444 Reset and clock control (RCC) Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Disable 1: Enable Bit 27 DBGEN: Debug support clock enable Set and cleared by software. 0: Disable 1: Enable Bit 26 UCPD2EN: UCPD2 clock enable Set and cleared by software.
Page 200 Reset and clock control (RCC) RM0444 Bit 17 USART2EN: USART2 clock enable Set and cleared by software. 0: Disable 1: Enable Bit 16 CRSEN: CRS clock enable Set and cleared by software. 0: Disable 1: Enable Bit 15 SPI3EN: SPI3 clock enable Set and cleared by software.
Page 201: Apb Peripheral Clock Enable Register 2(Rcc_Apbenr2)
RM0444 Reset and clock control (RCC) Bit 6 Reserved, must be kept at reset value. Bit 5 TIM7EN: TIM7 timer clock enable Set and cleared by software. 0: Disable 1: Enable Bit 4 TIM6EN: TIM6 timer clock enable Set and cleared by software. 0: Disable 1: Enable Bit 2 TIM4EN: TIM4 timer clock enable...
Page 202: I/O Port In Sleep Mode Clock Enable Register (Rcc_Iopsmenr)
Reset and clock control (RCC) RM0444 Bit 18 TIM17EN: TIM16 timer clock enable Set and cleared by software. 0: Disable 1: Enable Bit 17 TIM16EN: TIM16 timer clock enable Set and cleared by software. 0: Disable 1: Enable Bit 16 TIM15EN: TIM15 timer clock enable Set and cleared by software.
Page 203: Ahb Peripheral Clock Enable In Sleep/Stop Mode Register (Rcc_Ahbsmenr)
RM0444 Reset and clock control (RCC) GPIOE GPIOF GPIOD GPIOC GPIOB GPIOA SMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMEN SMEN SMEN SMEN SMEN 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to Section 1.4: Availability of peripherals.
Page 204 Reset and clock control (RCC) RM0444 SMEN SMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2 SRAM FLASH DMA1 SMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMEN SMEN SMEN SMEN 1.
Page 205: Apb Peripheral Clock Enable In Sleep/Stop Mode Register 1
RM0444 Reset and clock control (RCC) Bits 7:2 Reserved, must be kept at reset value. Bit 1 DMA2SMEN: DMA2 and DMAMUX clock enable during Sleep mode Set and cleared by software. 0: Disable 1: Enable Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral.
Page 206 Reset and clock control (RCC) RM0444 Bit 28 PWRSMEN: Power interface clock enable during Sleep mode Set and cleared by software. 0: Disable 1: Enable Bit 27 DBGSMEN: Debug support clock enable during Sleep mode Set and cleared by software. 0: Disable 1: Enable Bit 26 UCPD2SMEN: UCPD2 clock enable during Sleep mode...
Page 207 RM0444 Reset and clock control (RCC) Bit 17 USART2SMEN: USART2 clock enable during Sleep and Stop modes Set and cleared by software. 0: Disable 1: Enable Bit 16 CRSSMEN: CRS clock enable during Sleep and Stop modes Set and cleared by software. 0: Disable 1: Enable Bit 15 SPI3SMEN: SPI3 clock enable during Sleep mode...
Page 208: Apb Peripheral Clock Enable In Sleep/Stop Mode Register 2
Reset and clock control (RCC) RM0444 Bit 5 TIM7SMEN: TIM7 timer clock enable during Sleep mode Set and cleared by software. 0: Disable 1: Enable Bit 4 TIM6SMEN: TIM6 timer clock enable during Sleep mode Set and cleared by software. 0: Disable 1: Enable Bit 3 Reserved, must be kept at reset value.
Page 209: Peripherals Independent Clock Configuration Register (Rcc_Ccipr)
RM0444 Reset and clock control (RCC) Bit 18 TIM17SMEN: TIM16 timer clock enable during Sleep mode Set and cleared by software. 0: Disable 1: Enable Bit 17 TIM16SMEN: TIM16 timer clock enable during Sleep mode Set and cleared by software. 0: Disable 1: Enable Bit 16 TIM15SMEN: TIM15 timer clock enable during Sleep mode...
Page 210 Reset and clock control (RCC) RM0444 TIM15 TIM1 ADCSEL[1:0] Res. Res. LPTIM2SEL[1:0] LPTIM1SEL[1:0] Res. Res. RNGDIV[1:0] RNGSEL[1:0] LPUART2SEL USART3SEL USART2SEL LPUART1SEL USART1SEL I2C2I2S1SEL[1:0] I2C1SEL[1:0] Res. [1:0] [1:0] [1:0] [1:0] [1:0] 1. Only significant on devices integrating the corresponding peripheral supporting independent clock selection (or supporting the corresponding function), otherwise reserved.
Page 211 RM0444 Reset and clock control (RCC) Bits 19:18 LPTIM1SEL[1:0]: LPTIM1 clock source selection This bitfield is controlled by software to select LPTIM1 clock source as follows: 00: PCLK 01: LSI 10: HSI16 11: LSE Bits 17:16 Reserved, must be kept at reset value. Bits 15:14 I2C2I2S1SEL[1:0]: I2C2/I2S1 clock source selection This bitfield is controlled by software to select I2S1/I2C2 clock source as follows: 00: PCLK/SYSCLK...
Page 212: (Rcc_Ccipr2)
Reset and clock control (RCC) RM0444 Bits 5:4 USART3SEL[1:0]: USART3 clock source selection This bitfield is controlled by software to select USART2 clock source as follows: 00: PCLK 01: SYSCLK 10: HSI16 11: LSE Bits 3:2 USART2SEL[1:0]: USART2 clock source selection This bitfield is controlled by software to select USART2 clock source as follows: 00: PCLK 01: SYSCLK...
Page 213: Rtc Domain Control Register (Rcc_Bdcr)
RM0444 Reset and clock control (RCC) Bits 9:8 FDCANSEL[1:0]: FDCAN clock source selection This bitfield is controlled by software to select the FDCAN clock as follows: 00: PCLK 01: PLLQCLK 10: HSE 11: Reserved Bits 7:4 Reserved, must be kept at reset value. Bits 3:2 I2S2SEL[1:0]: I2S2 clock source selection This bitfield is controlled by software to select I2S2 clock source as follows: 00: SYSCLK...
Page 214 Reset and clock control (RCC) RM0444 Bits 31:26 Reserved, must be kept at reset value. Bit 25 LSCOSEL: Low-speed clock output selection Set and cleared by software to select the low-speed output clock: 0: LSI 1: LSE Bit 24 LSCOEN: Low-speed clock output (LSCO) enable Set and cleared by software.
Page 215: Control/Status Register (Rcc_Csr)
RM0444 Reset and clock control (RCC) Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: 00: low driving capability 01: medium-low driving capability 10: medium-high driving capability 11: high driving capability Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.
Page 216 Reset and clock control (RCC) RM0444 Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. 0: No illegal mode reset occurred 1: Illegal mode reset occurred This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared.
Page 217: Rcc Register Map
RM0444 Reset and clock control (RCC) Bits 22:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): 0: Not ready 1: Ready After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles.
Page 218 Reset and clock control (RCC) RM0444 Table 36. RCC register map and reset values (continued) Off- Register RCC_CIER 0x18 0 0 0 0 0 0 Reset value RCC_CIFR 0x1C 0 0 0 0 0 0 Reset value RCC_CICR 0x20 0 0 0 0 0 0 Reset value RCC_ IOPRSTR...
Page 219 RM0444 Reset and clock control (RCC) Table 36. RCC register map and reset values (continued) Off- Register RCC_ AHBENR 0x38 Reset value RCC_ APBENR1 0x3C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value...
Page 220 Reset and clock control (RCC) RM0444 Table 36. RCC register map and reset values (continued) Off- Register RCC_CCIPR 0x54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value RCC_CCIPR2 0x58...
Page 221: Clock Recovery System (Crs)
RM0444 Clock recovery system (CRS) Clock recovery system (CRS) This section applies to STM32G0B1 and STM32G0C1 devices only. Introduction The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-granularity trimmable RC oscillator HSI48. The CRS provides powerful means for oscillator output frequency evaluation, based on comparison with a selectable synchronization signal.
Page 222: Crs Functional Description
Clock recovery system (CRS) RM0444 Table 38. CRS internal input/output signals Internal signal name Signal type Description crs_sync_in_1 Input 00: GPIO AF selected as SYNC signal source crs_sync_in_2 Input 01: LSE selected as SYNC signal source crs_sync_in_3 Input 10: USB SOF selected as SYNC signal source (default) crs_sync_in_4 Input 11: Reserved...
Page 223: Frequency Error Measurement
RM0444 Clock recovery system (CRS) It is also possible to generate a synchronization event by software, by setting the SWSYNC bit in the CRS_CR register. 6.4.3 Frequency error measurement The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD value on each SYNC event.
Page 224: Frequency Error Evaluation And Automatic Trimming
Clock recovery system (CRS) RM0444 6.4.4 Frequency error evaluation and automatic trimming The measured frequency error is evaluated by comparing its value with a set of limits: – TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register –...
Page 225: Crs Low-Power Modes
RM0444 Clock recovery system (CRS) FELIM value The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics and its typical trimming step size. The optimal value corresponds to half of the trimming step size, expressed as a number of HSI48 oscillator clock ticks. The following formula can be used: FELIM = (f ) * STEP[%] / 100% / 2...
Page 226: Crs Registers
Clock recovery system (CRS) RM0444 CRS registers Refer to Section 1.2 on page 53 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed only by words (32-bit). 6.7.1 CRS control register (CRS_CR) Address offset: 0x00 Reset value: 0x0000 X000 (X=4 for products supporting 7-bit TRIM width, otherwise X=2) Res.
Page 227: Crs Configuration Register (Crs_Cfgr)
RM0444 Clock recovery system (CRS) Bit 2 ERRIE: Synchronization or trimming error interrupt enable 0: Synchronization or trimming error (ERRF) interrupt disabled 1: Synchronization or trimming error (ERRF) interrupt enabled Bit 1 SYNCWARNIE: SYNC warning interrupt enable 0: SYNC warning (SYNCWARNF) interrupt disabled 1: SYNC warning (SYNCWARNF) interrupt enabled Bit 0 SYNCOKIE: SYNC event OK interrupt enable 0: SYNC event OK (SYNCOKF) interrupt disabled...
Page 228: Crs Interrupt And Status Register (Crs_Isr)
Clock recovery system (CRS) RM0444 Bits 26:24 SYNCDIV[2:0]: SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 000: SYNC not divided (default) 001: SYNC divided by 2 010: SYNC divided by 4 011: SYNC divided by 8 100: SYNC divided by 16 101: SYNC divided by 32...
Page 229 RM0444 Clock recovery system (CRS) Bit 9 SYNCMISS: SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action has to be taken.
Page 230: Crs Interrupt Flag Clear Register (Crs_Icr)
Clock recovery system (CRS) RM0444 6.7.4 CRS interrupt flag clear register (CRS_ICR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYNC SYNC Res. Res. Res. Res.
Page 231: Crs Register Map
RM0444 Clock recovery system (CRS) 6.7.5 CRS register map Table 41. CRS register map and reset values Offset Register TRIM[5:0] CRS_CR 0x00 Reset value SYNC SYNC CRS_CFGR FELIM[7:0] RELOAD[15:0] 0x04 [1:0] [2:0] Reset value CRS_ISR FECAP[15:0] 0x08 Reset value CRS_ICR 0x0C Reset value Refer to...
Page 232: General-Purpose I/Os (Gpio)
General-purpose I/Os (GPIO) RM0444 General-purpose I/Os (GPIO) Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Page 233: Table 42. Port Bit Configuration Table
RM0444 General-purpose I/Os (GPIO) Figure 17 shows the basic structures of a standard I/O port bit. Table 42 gives the possible port bit configurations. Figure 17. Basic structure of an I/O port bit To/from on-chip Analog input/output peripherals, power control Digital input and EXTI On/off...
Page 234: General-Purpose I/O (Gpio)
General-purpose I/Os (GPIO) RM0444 Table 42. Port bit configuration table (continued) MODE(i) OSPEED(i) PUPD(i) OTYPE(i) I/O configuration [1:0] [1:0] [1:0] Input Floating Input Input Reserved (input floating) Input/output Analog Reserved 1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.
Page 235: I/O Port Control Registers
RM0444 General-purpose I/Os (GPIO) Each I/O pin has a multiplexer with up to eight alternate function inputs (AF0 to AF7) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers: •...
Page 236: I/O Data Bitwise Handling
General-purpose I/Os (GPIO) RM0444 Section 7.4.5: GPIO port input data register (GPIOx_IDR) (x = A to F) Section 7.4.6: GPIO port output data register (GPIOx_ODR) (x = A to F) for the register descriptions. 7.3.5 I/O data bitwise handling The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR).
Page 237: External Interrupt/Wakeup Lines
RM0444 General-purpose I/Os (GPIO) thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O. To know which functions are multiplexed on each GPIO pin refer to the device datasheet.
Page 238: Output Configuration
General-purpose I/Os (GPIO) RM0444 7.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) –...
Page 239: Analog Configuration
RM0444 General-purpose I/Os (GPIO) Figure 20. Alternate function configuration- Analog input/output To/from on-chip Alternate function input peripheral Read DDIOx TTL Schmitt trigger on/off Pull Write Input driver I/O pin Output driver DDIOx on/off Pull P-MOS down Output Read/write control N-MOS Push-pull From on-chip Alternate function output...
Page 240: Using The Hse Or Lse Oscillator Pins As Gpios
General-purpose I/Os (GPIO) RM0444 7.3.13 Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.
Page 241: Gpio Registers
RM0444 General-purpose I/Os (GPIO) GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The peripheral registers can be written in word, half word or byte mode. 7.4.1 GPIO port mode register (GPIOx_MODER) (x =A to F)
Page 242: Gpio Port Output Speed Register (Gpiox_Ospeedr)
General-purpose I/Os (GPIO) RM0444 7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to F) Address offset: 0x08 Reset value: 0x0C00 0000 (for port A) Reset value: 0x0000 0000 (for other ports) OSPEED15 OSPEED14 OSPEED13 OSPEED12 OSPEED11 OSPEED10 OSPEED9 OSPEED8 [1:0] [1:0]...
Page 243: Gpio Port Input Data Register (Gpiox_Idr)
RM0444 General-purpose I/Os (GPIO) 7.4.5 GPIO port input data register (GPIOx_IDR) (x = A to F) Address offset: 0x10 Reset value: 0x0000 XXXX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ID15 ID14 ID13 ID12...
Page 244: Gpio Port Configuration Lock Register (Gpiox_Lckr)
General-purpose I/Os (GPIO) RM0444 BS15 BS14 BS13 BS12 BS11 BS10 Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Resets the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority.
Page 245: (X = A To F)
RM0444 General-purpose I/Os (GPIO) Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 246: (X = A To F)
General-purpose I/Os (GPIO) RM0444 7.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to F) Address offset: 0x24 Reset value: 0x0000 0000 AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0] AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0] Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: 1000: Reserved...
Page 247: Gpio Register Map
RM0444 General-purpose I/Os (GPIO) 7.4.12 GPIO register map The following table gives the GPIO register map and reset values. Table 43. GPIO register map and reset values Offset Register name GPIOx_MODER 0x00 Reset value port A 1 1 1 1 1 1 1 1 1 1 1 1 Reset value 1 1 1 1...
Page 248: System Configuration Controller (Syscfg)
System configuration controller (SYSCFG) RM0444 System configuration controller (SYSCFG) The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Enabling/disabling I C Fast Mode Plus on some I/O ports • Enabling/disabling the analog switch booster •...
Page 249 RM0444 System configuration controller (SYSCFG) Bits 31:25 Reserved, must be kept at reset value. Bit 24 I2C3_FMP: Fast Mode Plus (FM+) enable for I2C3 This bit is set and cleared by software. It enables I C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers.
Page 250 System configuration controller (SYSCFG) RM0444 Bit 18 I2C_PB8_FMP: Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I C FM+ driving capability on PB8 I/O port. 0: Disable 1: Enable With this bit in disable state, the I C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits.
Page 251: Syscfg Configuration Register 2 (Syscfg_Cfgr2)
RM0444 System configuration controller (SYSCFG) Bit 5 IR_POL: IR output polarity selection 0: Output of IRTIM (IR_OUT) is not inverted 1: Output of IRTIM (IR_OUT) is inverted Bit 4 PA12_RMP: PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port.
Page 252 System configuration controller (SYSCFG) RM0444 Bits 31:24 Reserved, must be kept at reset value Bit 23 PB2_CDEN: PB2 clamping diode enable bit This bit is set and cleared by software. It enables (connects) a clamping diode to V on PB2 pin.
Page 253: Syscfg Interrupt Line 0 Status Register (Syscfg_Itline0)
RM0444 System configuration controller (SYSCFG) Bits 7:4 Reserved, must be kept at reset value. Bit 3 ECC_LOCK: ECC error lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the Flash ECC 2-bit error detection signal connection to TIM1/15/16/17 Break input.
Page 254: Syscfg Interrupt Line 1 Status Register (Syscfg_Itline1)
System configuration controller (SYSCFG) RM0444 8.1.4 SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1) Address offset: 0x84 System reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PVMOUT Res. Res. Res.
Page 255: Syscfg Interrupt Line 4 Status Register (Syscfg_Itline4)
RM0444 System configuration controller (SYSCFG) Bits 31:2 Reserved, must be kept at reset value. Bit 1 FLASH_ECC: Flash interface ECC interrupt request pending Bit 0 FLASH_ITF: Flash interface interrupt request pending 8.1.7 SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4) Address offset: 0x90 System reset value: 0x0000 0000 Res.
Page 256: Syscfg Interrupt Line 5 Status Register (Syscfg_Itline5)
System configuration controller (SYSCFG) RM0444 8.1.8 SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5) Address offset: 0x94 System reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 257: Syscfg Interrupt Line 8 Status Register (Syscfg_Itline8)
RM0444 System configuration controller (SYSCFG) Bits 31:12 Reserved, must be kept at reset value. Bit 11 EXTI15: EXTI line 15 interrupt request pending Bit 10 EXTI14: EXTI line 14 interrupt request pending Bit 9 EXTI13: EXTI line 13 interrupt request pending Bit 8 EXTI12: EXTI line 12 interrupt request pending Bit 7 EXTI11: EXTI line 11 interrupt request pending Bit 6 EXTI10: EXTI line 10 interrupt request pending...
Page 258: Syscfg Interrupt Line 10 Status Register (Syscfg_Itline10)
System configuration controller (SYSCFG) RM0444 DMA1_ Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:1 Reserved, must be kept at reset value. Bit 0 DMA1_CH1: DMA1 channel 1 interrupt request pending 8.1.13 SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10) Address offset: 0xA8 System reset value: 0x0000 0000...
Page 259: Syscfg Interrupt Line 12 Status Register (Syscfg_Itline12)
RM0444 System configuration controller (SYSCFG) Bit 4 DMA1_CH7: DMA1 channel 7 interrupt request pending Bit 3 DMA1_CH6 DMA1 channel 6 interrupt request pending Bit 2 DMA1_CH5: DMA1 channel 5 interrupt request pending Bit 1 DMA1_CH4: DMA1 channel 4 interrupt request pending Bit 0 DMAMUX: DMAMUX interrupt request pending 8.1.15 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12)
Page 260: Syscfg Interrupt Line 14 Status Register (Syscfg_Itline14)
System configuration controller (SYSCFG) RM0444 8.1.17 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14) Address offset: 0xB8 System reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM1_ Res. Res. Res.
Page 261: Syscfg Interrupt Line 17 Status Register (Syscfg_Itline17)
RM0444 System configuration controller (SYSCFG) 8.1.20 SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17) Address offset: 0xC4 System reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 262: Syscfg Interrupt Line 20 Status Register (Syscfg_Itline20)
System configuration controller (SYSCFG) RM0444 Bits 31:1 Reserved, must be kept at reset value. Bit 0 TIM14: Timer 14 interrupt request pending 8.1.23 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20) Address offset: 0xD0 System reset value: 0x0000 0000 Res. Res. Res.
Page 263: Syscfg Interrupt Line 23 Status Register (Syscfg_Itline23)
RM0444 System configuration controller (SYSCFG) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FDCAN FDCAN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM17 2_IT0 1_IT0 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability peripherals.
Page 264: Syscfg Interrupt Line 25 Status Register (Syscfg_Itline25)
System configuration controller (SYSCFG) RM0444 8.1.28 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) Address offset: 0xE4 System reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 265: Syscfg Interrupt Line 28 Status Register (Syscfg_Itline28)
RM0444 System configuration controller (SYSCFG) 8.1.31 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) Address offset: 0xF0 System reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPUAR Res. Res. Res.
Page 266: Syscfg Interrupt Line 31 Status Register (Syscfg_Itline31)
System configuration controller (SYSCFG) RM0444 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1. Only significant on devices integrating CEC, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Page 267 RM0444 System configuration controller (SYSCFG) Table 44. SYSCFG register map and reset values (continued) Offset Register SYSCFG_CFGR2 0x18 Reset value 0x1D to Reserved Reserved 0x7F SYSCFG_ITLINE0 0x80 Reset value SYSCFG_ITLINE1 0x84 Reset value SYSCFG_ITLINE2 0x88 Reset value SYSCFG_ITLINE3 0x8C Reset value SYSCFG_ITLINE4 0x90 Reset value...
Page 268 System configuration controller (SYSCFG) RM0444 Table 44. SYSCFG register map and reset values (continued) Offset Register SYSCFG_ITLINE11 0xAC Reset value SYSCFG_ITLINE12 0xB0 Reset value SYSCFG_ITLINE13 0xB4 Reset value SYSCFG_ITLINE14 0xB8 Reset value SYSCFG_ITLINE15 0xBC Reset value SYSCFG_ITLINE16 0xC0 Reset value SYSCFG_ITLINE17 0xC4 Reset value...
Page 269 RM0444 System configuration controller (SYSCFG) Table 44. SYSCFG register map and reset values (continued) Offset Register SYSCFG_ITLINE26 0xE8 Reset value SYSCFG_ITLINE27 0xEC Reset value SYSCFG_ITLINE28 0xF0 Reset value SYSCFG_ITLINE29 0xF4 Reset value SYSCFG_ITLINE30 0xF8 Reset value SYSCFG_ITLINE31 0xFC Reset value Refer to Section 2.2 on page 58 for the register boundary addresses.
Page 270: Interconnect Matrix
Interconnect matrix RM0444 Interconnect matrix Introduction Several peripherals have direct connections between them. This allows autonomous communication and/or synchronization between peripherals, saving CPU resources thus power consumption. In addition, these hardware connections remove software latency and allow design of predictable systems. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run, Low-power sleep, Stop 0, and Stop 1 modes.
Page 271: Interconnection Details
RM0444 Interconnect matrix (1)(2) Table 45. Interconnect matrix (continued) Destination Source VREFINT 9.3.8 9.3.5 9.3.5 9.3.5 9.3.5 9.3.5 9.3.5 9.3.5 MCO2 9.3.5 9.3.5 EXTI 9.3.2 9.3.4 RTC and 9.3.5 9.3.5 9.3.6 9.3.6 TAMP COMP1 9.3.9 9.3.9 9.3.9 9.3.9 9.3.9 9.3.9 9.3.9 9.3.6 9.3.6...
Page 272: From Tim1, Tim2, Tim3, Tim4, Tim6, Tim15, And Exti, To Adc
Interconnect matrix RM0444 Triggering signals The output (from master) is on signal TIMx_TRGO (and TIMx_TRGOx), following a configurable timer event. With TIM14, TIM16, and TIM17 timers that do not have a trigger output, the output compare 1 is used instead. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.
Page 273: From Tim1, Tim2, Tim3, Tim4, Tim6, Tim7, Tim15, Lptim1, Lptim2
RM0444 Interconnect matrix Triggering signals The output (from ADC) is on signals ADCn_AWDx_OUT n = 1, 2, 3 (for ADC) x = 1, 2, 3 (three watchdogs per ADC) and the input (to timer) on signal TIMx_ETR (external trigger). Relevant power modes This interconnection operates in Run, Sleep, Low-power run, and Low-power sleep power modes.
Page 274: From Rtc, Tamp, Comp1, Comp2, And Comp3 To Lptim1
Interconnect matrix RM0444 9.3.6 From RTC, TAMP, COMP1, COMP2, and COMP3 to LPTIM1 and LPTIM2 Purpose RTC alarm A/B, TAMP1/2 input detection, COMP1/2_OUT and GPIO alternate function can be used as trigger to start LPTIM counters LPTIM1/2. Triggering signals This trigger feature is described in Section 26.4.7: Trigger multiplexer (and following sections).
Page 275: From Comp1, Comp2, And Comp3 To Tim1, Tim2, Tim3, Tim4, Tim15
RM0444 Interconnect matrix More information is in: • Section 15.2: ADC main features • Section 15.3.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD) • Figure 15.9: Temperature sensor and internal reference voltage • Figure 15.10: Battery voltage monitoring Relevant power modes These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.
Page 276: From Tim16, Tim17, Usart1, And Usart4, To Irtim
Interconnect matrix RM0444 List of possible source of break are described in: • Section 21.3.16: Using the break function (TIM1) • Section 25.4.13: Using the break function (TIM15/TIM16/TIM17) • Figure 236: TIM15 block diagram • Figure 237: TIM16/TIM17 block diagram Relevant power modes These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.
Page 277: Direct Memory Access Controller (Dma)
RM0444 Direct memory access controller (DMA) Direct memory access controller (DMA) 10.1 Introduction The direct memory access (DMA) controller is a bus master and system peripheral. The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU. The DMA controller features a single AHB master architecture.
Page 278: Dma Implementation
Direct memory access controller (DMA) RM0444 10.3 DMA implementation 10.3.1 The devices incorporate one or two DMA controller instances. The following implementation table shows the number of DMA channels for either instance. A dash indicates that the instance is not implemented. Table 46.
Page 279: Dma Pins And Internal Signals
RM0444 Direct memory access controller (DMA) The DMA block diagram is shown in the figure below. Figure 22. DMA block diagram Ch 1 Ch 2 AHB master interface Ch 7 dma_req [1..7] Arbiter dma_ack [1..7] Interrupt AHB slave interface interface dma_it[1..7] MSv48187V1 The DMA controller performs direct memory transfer by sharing the AHB system bus with...
Page 280: Dma Arbitration
Direct memory access controller (DMA) RM0444 A DMA block transfer may be requested from a peripheral, or triggered by the software in case of memory-to-memory transfer. After an event, the following steps of a single DMA transfer occur: The peripheral sends a single DMA request signal to the DMA controller. The DMA controller serves the request, depending on the priority of the channel associated to this peripheral request.
Page 281: Dma Channels
RM0444 Direct memory access controller (DMA) The priorities are managed in two stages: • software: priority of each channel is configured in the DMA_CCRx register, to one of the four different levels: – very high – high – medium – •...
Page 282 Direct memory access controller (DMA) RM0444 Channel configuration procedure The following sequence is needed to configure a DMA channel x: Set the peripheral register address in the DMA_CPARx register. The data is moved from/to this address to/from the memory after the peripheral event, or after the channel is enabled in memory-to-memory mode.
Page 283 RM0444 Direct memory access controller (DMA) register content may not correctly reflect the remaining data transfers versus the aborted source and destination buffer/register. • Abort and restart a channel This corresponds to the software sequence: disable an active channel, then reconfigure the channel and enable it again.
Page 284: Dma Data Width, Alignment And Endianness
Direct memory access controller (DMA) RM0444 Peripheral-to-peripheral mode Any DMA channel can operate in peripheral-to-peripheral mode: • when the hardware request from a peripheral is selected to trigger the DMA channel This peripheral is the DMA initiator and paces the data transfer from/to this peripheral to/from a register belonging to another memory-mapped peripheral (this one being not configured in DMA mode).
Page 285: Table 48. Programmable Data Width And Endian Behavior (When Pinc = Minc = 1)
RM0444 Direct memory access controller (DMA) Table 48. Programmable data width and endian behavior (when PINC = MINC = 1) Source Destinat Destination port ion port Source content: Number width content: width address / data of data (PSIZE address / data (MSIZE items to DMA transfers...
Page 286: Dma Error Management
Direct memory access controller (DMA) RM0444 Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB transfer as described below: •...
Page 287: Dma Interrupt Status Register (Dma_Isr)
RM0444 Direct memory access controller (DMA) 10.6.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Every status bit is cleared by hardware when the software sets the corresponding clear bit or the corresponding global clear bit CGIFx, in the DMA_IFCR register. Res.
Page 288 Direct memory access controller (DMA) RM0444 Bit 17 TCIF5: transfer complete (TC) flag for channel 5 0: no TC event 1: a TC event occurred Bit 16 GIF5: global interrupt flag for channel 5 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 15 TEIF4: transfer error (TE) flag for channel 4 0: no TE event...
Page 289: Dma Interrupt Flag Clear Register (Dma
RM0444 Direct memory access controller (DMA) Bit 2 HTIF1: half transfer (HT) flag for channel 1 0: no HT event 1: a HT event occurred Bit 1 TCIF1: transfer complete (TC) flag for channel 1 0: no TC event 1: a TC event occurred Bit 0 GIF1: global interrupt flag for channel 1 0: no TE, HT or TC event 1: a TE, HT or TC event occurred...
Page 290: Dma Channel X Configuration Register (Dma_Ccrx)
Direct memory access controller (DMA) RM0444 Bit 17 CTCIF5: transfer complete flag clear for channel 5 Bit 16 CGIF5: global interrupt flag clear for channel 5 Bit 15 CTEIF4: transfer error flag clear for channel 4 Bit 14 CHTIF4: half transfer flag clear for channel 4 Bit 13 CTCIF4: transfer complete flag clear for channel 4 Bit 12 CGIF4: global interrupt flag clear for channel 4 Bit 11 CTEIF3: transfer error flag clear for channel 3...
Page 291 RM0444 Direct memory access controller (DMA) Bits 31:15 Reserved, must be kept at reset value. Bit 14 MEM2MEM: memory-to-memory mode 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Page 292 Direct memory access controller (DMA) RM0444 Bit 7 MINC: memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0.
Page 293: Dma Channel X Number Of Data To Transfer Register (Dma_Cndtrx)
RM0444 Direct memory access controller (DMA) Bit 2 HTIE: half transfer interrupt enable 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). Bit 1 TCIE: transfer complete interrupt enable 0: disabled 1: enabled...
Page 294: Dma Channel X Peripheral Address Register (Dma_Cparx)
Direct memory access controller (DMA) RM0444 10.6.5 DMA channel x peripheral address register (DMA_CPARx) Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 PA[31:16] PA[15:0] Bits 31:0 PA[31:0]: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written.
Page 295: Dma Register Map
RM0444 Direct memory access controller (DMA) Bits 31:0 MA[31:0]: peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address.
Page 296 Direct memory access controller (DMA) RM0444 Table 50. DMA register map and reset values (continued) Offset Register DMA_CCR3 0x030 Reset value DMA_CNDTR3 NDTR[15:0] 0x034 Reset value DMA_CPAR3 PA[31:0] 0x038 Reset value DMA_CMAR3 MA[31:0] 0x03C Reset value 0x040 Reserved Reserved. DMA_CCR4 0x044 Reset value DMA_CNDTR4...
Page 297 RM0444 Direct memory access controller (DMA) Table 50. DMA register map and reset values (continued) Offset Register DMA_CNDTR7 NDTR[15:0] 0x084 Reset value DMA_CPAR7 PA[31:0] 0x088 Reset value DMA_CMAR7 MA[31:0] 0x08C Reset value Refer to Section 2.2 for the register boundary addresses. RM0444 Rev 5 297/1390...
Page 298: Dma Request Multiplexer (Dmamux)
DMA request multiplexer (DMAMUX) RM0444 DMA request multiplexer (DMAMUX) 11.1 Introduction A peripheral indicates a request for DMA transfer by setting its DMA request signal. The DMA request is pending until it is served by the DMA controller that generates a DMA acknowledge signal, and the corresponding DMA request signal is deasserted.
Page 299: Dmamux Main Features
RM0444 DMA request multiplexer (DMAMUX) 11.2 DMAMUX main features • up to 12-channel programmable DMA request line multiplexer output • 4-channel DMA request generator • 23 trigger inputs to DMA request generator • 23 synchronization inputs • Per DMA request generator channel: –...
Page 300: Table 52. Dmamux: Assignment Of Multiplexer Inputs To Resources
DMA request multiplexer (DMAMUX) RM0444 Table 52. DMAMUX: assignment of multiplexer inputs to resources request request request Resource Resource Resource input input input dmamux_req_gen0 TIM2_CH2 USART2_TX dmamux_req_gen1 TIM2_CH3 USART3_RX dmamux_req_gen2 TIM2_CH4 USART3_TX dmamux_req_gen3 TIM2_TRIG USART4_RX TIM2_UP USART4_TX AES_IN TIM3_CH1 UCPD1_RX AES_OUT TIM3_CH2 UCPD1_TX...
Page 301: Table 54. Dmamux: Assignment Of Synchronization Inputs To Resources
RM0444 DMA request multiplexer (DMAMUX) Table 53. DMAMUX: assignment of trigger inputs to resources (continued) Trigger input Resource Trigger input Resource EXTI LINE6 dmamux_evt2 EXTI LINE7 dmamux_evt3 EXTI LINE8 LPTIM1_OUT EXTI LINE9 LPTIM2_OUT EXTI LINE10 TIM14_OC EXTI LINE11 Reserved Table 54. DMAMUX: assignment of synchronization inputs to resources Sync.
Page 302: Dmamux Functional Description
DMA request multiplexer (DMAMUX) RM0444 11.4 DMAMUX functional description 11.4.1 DMAMUX block diagram Figure 23 shows the DMAMUX block diagram. Figure 23. DMAMUX block diagram 32-bit AHB bus dmamux_hclk DMAMUX Request multiplexer AHB slave Channel m interface DMAMUX_CmCR Channel 1 Channel 0 DMA requests DMAMUX_C0CR...
Page 303: Dmamux Signals
RM0444 DMA request multiplexer (DMAMUX) 11.4.2 DMAMUX signals Table 55 lists the DMAMUX signals. Table 55. DMAMUX signals Signal name Description dmamux_hclk DMAMUX AHB clock dmamux_req_inx DMAMUX DMA request line inputs from peripherals dmamux_trgx DMAMUX DMA request triggers inputs (to request generator sub-block) dmamux_req_genx DMAMUX request generator sub-block channels outputs DMAMUX request multiplexer sub-block inputs (from peripheral...
Page 304 DMA request multiplexer (DMAMUX) RM0444 Caution: A same non-null DMAREQ_ID can be assigned to two different channels only if the application ensures that these channels are not requested to be served at the same time. In other words, if two different channels receive a same asserted hardware request at the same time, an unpredictable DMA hardware behavior occurs.
Page 305: Figure 24. Synchronization Mode Of The Dmamux Request Line Multiplexer Channel
RM0444 DMA request multiplexer (DMAMUX) Figure 24. Synchronization mode of the DMAMUX request line multiplexer channel Selected DMA request line transferred to the output DMA requests served DMA request pending Selected dmamux_reqx Not pending dmamux_syncx dmamux_req_outx DMA request counter dmamux_evtx DMA request counter underrun Synchronization event DMA request counter auto-reload to NBREQ...
Page 306: Dmamux Request Generator
DMA request multiplexer (DMAMUX) RM0444 Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request. Note: A synchronization event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles. Upon writing into DMAMUX_CxCR register, the synchronization events are masked during three AHB clock cycles.
Page 307: Dmamux Interrupts
RM0444 DMA request multiplexer (DMAMUX) Note: The GNBREQ field value must be written by software only when the enable GE bit of the corresponding generator channel x is disabled. A trigger event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles.
Page 308: Dmamux Registers
DMA request multiplexer (DMAMUX) RM0444 11.6 DMAMUX registers Refer to the table containing register boundary addresses for the DMAMUX base address. DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word. The address must be aligned with the data size. 11.6.1 DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR)
Page 309: Dmamux Request Line Multiplexer Interrupt Channel Status Register
RM0444 DMA request multiplexer (DMAMUX) Bit 7 Reserved, must be kept at reset value. Bits 6:0 DMAREQ_ID[6:0]: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 11.6.2 DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR) Address offset: 0x080 Reset value: 0x0000 0000...
Page 310: Dmamux Request Generator Channel X Configuration Register (Dmamux_Rgxcr)
DMA request multiplexer (DMAMUX) RM0444 11.6.4 DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) Address offset: 0x100 + 0x04 * x (x = 0 to 3) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] GPOL[1:0] Res.
Page 311: Dmamux Request Generator Interrupt Status Register (Dmamux_Rgsr)
RM0444 DMA request multiplexer (DMAMUX) 11.6.5 DMAMUX request generator interrupt status register (DMAMUX_RGSR) Address offset: 0x140 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 312: Dmamux Register Map
DMA request multiplexer (DMAMUX) RM0444 11.6.7 DMAMUX register map The following table summarizes the DMAMUX registers and reset values. Refer to the register boundary address table for the DMAMUX register base address. Table 57. DMAMUX register map and reset values Offset Register DMAREQ_ID[6:0]...
Page 313 RM0444 DMA request multiplexer (DMAMUX) Table 57. DMAMUX register map and reset values Offset Register DMAMUX_RG1CR GNBREQ[4:0] SIG_ID[4:0] 0x104 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAMUX_RG2CR GNBREQ[4:0] SIG_ID[4:0] 0x108 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAMUX_RG3CR...
Page 314: Nested Vectored Interrupt Controller (Nvic)
Nested vectored interrupt controller (NVIC) RM0444 Nested vectored interrupt controller (NVIC) 12.1 Main features ® • 32 maskable interrupt channels (not including the sixteen Cortex -M0+ interrupt lines) • 4 programmable priority levels (2 bits of interrupt priority are used) •...
Page 315 RM0444 Nested vectored interrupt controller (NVIC) Table 58. Vector table (continued) Type of Position Priority Acronym Description Address priority 0x0000_0030 Reserved 0x0000_0034 settable PendSV_Handler Pendable request for system service 0x0000_0038 settable SysTick_Handler System tick timer 0x0000_003C settable WWDG Window watchdog interrupt 0x0000_0040 Power voltage detector interrupt settable...
Page 316 Nested vectored interrupt controller (NVIC) RM0444 Table 58. Vector table (continued) Type of Position Priority Acronym Description Address priority I2C1 global interrupt (combined with settable I2C1 0x0000_009C EXTI 23) settable I2C2 / I2C3 I2C2 and I2C3 global interrupt 0x0000_00A0 settable SPI1 SPI1 global interrupt 0x0000_00A4...
Page 317: Extended Interrupt And Event Controller (Exti)
RM0444 Extended interrupt and event controller (EXTI) Extended interrupt and event controller (EXTI) The Extended interrupt and event controller (EXTI) manages the CPU and system wakeup through configurable and direct event inputs (lines). It provides wakeup requests to the power control, and generates an interrupt request to the CPU NVIC and events to the CPU event input.
Page 318: Table 59. Exti Signal Overview
Extended interrupt and event controller (EXTI) RM0444 Figure 26. EXTI block diagram AHB interface Registers hclk exti[15:0] To interconnect IOPort sys_wakeup c_wakeup Configurable event(15:0) it_exti_per(y)* Direct event(x) or configurable event(y) Event Wakeup c_evt_exti c_event Trigger Masking Pulse events rxev c_evt_rst c_fclk Interrupt Direct event(x)
Page 319: Exti Connections Between Peripherals And Cpu
RM0444 Extended interrupt and event controller (EXTI) 13.2.1 EXTI connections between peripherals and CPU The peripherals able to generate wakeup or interrupt events when the system is in Stop mode are connected to the EXTI. • Peripheral wakeup signals that generate a pulse or that do not have an interrupt status bits in the peripheral, are connect to an EXTI configurable line.
Page 320: Exti Configurable Event Input Wakeup
Extended interrupt and event controller (EXTI) RM0444 Table 61. EXTI event input configurations and register control Event input Logic implementation type Configurable Configurable event input wakeup logic Direct Direct event input wakeup logic 13.3.1 EXTI configurable event input wakeup Figure 27 is a detailed representation of the logic associated with configurable event inputs which wake up the CPU sub-system bus clocks and generated an EXTI pending flag and interrupt to the CPU and or a CPU wakeup event.
Page 321: Exti Direct Event Input Wakeup
RM0444 Extended interrupt and event controller (EXTI) Note: A detected configurable event interrupt pending request can be cleared by the CPU. The system cannot enter low-power modes as long as an interrupt pending request is active. 13.3.2 EXTI direct event input wakeup Figure 28 is a detailed representation of the logic associated with direct event inputs waking up the system.
Page 322: Table 62. Exti Line Connections
Extended interrupt and event controller (EXTI) RM0444 Figure 29. EXTI GPIO mux EXTI_EXTICR1.EXTI0 EXTI_EXTICR1.EXTI1 EXTI_EXTICR4.EXTI15 PA15 PB15 PC15 EXTI0 EXTI1 EXTI15 Px15 MS44726V1 The EXTIs mux outputs are available as output signals from the EXTI, to trigger other functional blocks. The EXTI mux outputs are available independently of mask setting through the EXTI_IMR and EXTI_EMR registers.
Page 323: Exti Functional Behavior
RM0444 Extended interrupt and event controller (EXTI) Table 62. EXTI line connections (continued) EXTI line Line source Line type monitoring configurable Direct DDIO2 LPUART2 wakeup Direct 13.4 EXTI functional behavior The direct event inputs are enabled in the respective peripheral generating the wakeup event.
Page 324: Exti Registers
Extended interrupt and event controller (EXTI) RM0444 13.5 EXTI registers The EXTI register map is divided in the following sections: Table 64. EXTI register map sections Address Description 0x000 - 0x01C General configurable event [31:0] configuration 0x060 - 0x06C EXTI I/O port multiplexer 0x080 - 0x0BC CPU input event configuration All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit)
Page 325: Exti Falling Trigger Selection Register 1 (Exti_Ftsr1)
RM0444 Extended interrupt and event controller (EXTI) 2. The configurable lines are edge triggered, no glitch must be generated on these inputs. If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set. Rising edge trigger can be set for a line with falling edge trigger enabled.
Page 326: Exti Rising Edge Pending Register 1 (Exti_Rpr1)
Extended interrupt and event controller (EXTI) RM0444 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI9 SWI8 SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 SWI1 SWI0 Bits 31:21 Reserved, must be kept at reset value. Bit 20 SWI20: Software rising edge event trigger on line 20 Setting this bit by software triggers a rising edge event on the corresponding line, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings.
Page 327: Exti Falling Edge Pending Register 1 (Exti_Fpr1)
RM0444 Extended interrupt and event controller (EXTI) Bits 31:21 Reserved, must be kept at reset value. Bit 20 RPIF20: Rising edge event pending for configurable line 20 This bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line.
Page 328: Exti Rising Trigger Selection Register 2 (Exti_Rtsr2)
Extended interrupt and event controller (EXTI) RM0444 Bit 20 FPIF20: Falling edge event pending for configurable line 20 This bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. This bit is cleared by writing 1 into it. 0: No falling edge trigger request occurred 1: Falling edge trigger request occurred The FPIF20 bit is only available in STM32G0B1xx and STM32G0C1xx.
Page 329: Exti Software Interrupt Event Register 2 (Exti_Swier2)
RM0444 Extended interrupt and event controller (EXTI) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:3 Reserved, must be kept at reset value. Bit 2 FT2: Falling trigger event configuration bit of configurable line 34 This bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
Page 330: Exti Falling Edge Pending Register 2 (Exti_Fpr2)
Extended interrupt and event controller (EXTI) RM0444 Reset value: 0x0000 0000 Contains only register bits for configurable events. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 331 RM0444 Extended interrupt and event controller (EXTI) Reset value: 0x0000 0000 EXTIm fields contain only the number of bits in line with the nb_ioport configuration. EXTIm+3[7:0] EXTIm+2[7:0] EXTIm+1[7:0] EXTIm[7:0] Bits 31:24 EXTIm+3[7:0]: EXTIm+3 GPIO port selection (m = 4 * (x - 1)) These bits are written by software to select the source input for EXTIm+3 external interrupt.
Page 332: Exti Cpu Wakeup With Interrupt Mask Register (Exti_Imr1)
Extended interrupt and event controller (EXTI) RM0444 13.5.12 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) Address offset: 0x080 (EXTI_IMR1) Reset value: 0xFFF8 0000 Contains register bits for configurable events and direct events. The reset value is set such as to, by default, enable interrupt from direct lines, and disable interrupt from configurable lines.
Page 333: Exti Cpu Wakeup With Interrupt Mask Register (Exti_Imr2)
RM0444 Extended interrupt and event controller (EXTI) 13.5.14 EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) Address offset: 0x090 (EXTI_IMR2) Reset value: 0xFFFF FFFF Contains register bits for configurable events and direct events. The reset value is set such as to, by default, enable interrupt from direct lines, and disable interrupt from configurable lines.
Page 334: Exti Register Map
Extended interrupt and event controller (EXTI) RM0444 Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 EMx: CPU wakeup with event generation mask on line x (x = 35 to 32) Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line.
Page 335 RM0444 Extended interrupt and event controller (EXTI) Table 65. EXTI controller register map and reset values (continued) Offset Register EXTI_EXTICR1 EXTI3[7:0] EXTI2[7:0] EXTI1[7:0] EXTI0[7:0] 0x060 Reset value EXTI_EXTICR2 EXTI7[7:0] EXTI6[7:0] EXTI5[7:0] EXTI4[7:0] 0x064 Reset value EXTI_EXTICR3 EXTI11[7:0] EXTI10[7:0] EXTI9[7:0] EXTI8[7:0] 0x068 Reset value EXTI_EXTICR4...
Page 336: Cyclic Redundancy Check Calculation Unit (Crc)
Cyclic redundancy check calculation unit (CRC) RM0444 Cyclic redundancy check calculation unit (CRC) 14.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 337: Crc Functional Description
RM0444 Cyclic redundancy check calculation unit (CRC) 14.3 CRC functional description 14.3.1 CRC block diagram Figure 30. CRC calculation unit block diagram 32-bit AHB bus 32-bit (read access) Data register (output) crc_hclk CRC computation 32-bit (write access) Data register (input) MS19882V2 14.3.2 CRC internal signals...
Page 338 Cyclic redundancy check calculation unit (CRC) RM0444 The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: •...
Page 339: Crc Registers
RM0444 Cyclic redundancy check calculation unit (CRC) 14.4 CRC registers 14.4.1 CRC data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF DR[31:16] DR[15:0] Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read.
Page 340: Crc Control Register (Crc_Cr)
Cyclic redundancy check calculation unit (CRC) RM0444 14.4.3 CRC control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_ Res. Res. Res. Res. Res.
Page 341: Crc Initial Value (Crc_Init)
RM0444 Cyclic redundancy check calculation unit (CRC) 14.4.4 CRC initial value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF CRC_INIT[31:16] CRC_INIT[15:0] Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value This register is used to write the CRC initial value. 14.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C1 1DB7 POL[31:16]...
Page 342: Crc Register Map
Cyclic redundancy check calculation unit (CRC) RM0444 14.4.6 CRC register map Table 67. CRC register map and reset values Register Offset name CRC_DR DR[31:0] 0x00 Reset value CRC_IDR IDR[31:0] 0x04 Reset value CRC_CR 0x08 Reset value CRC_INIT CRC_INIT[31:0] 0x10 Reset value CRC_POL POL[31:0] 0x14...
Page 343: Analog-To-Digital Converter (Adc)
RM0444 Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) 15.1 Introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external and 3 internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode.
Page 344: Adc Main Features
Analog-to-digital converter (ADC) RM0444 15.2 ADC main features • High performance – 12-bit, 10-bit, 8-bit or 6-bit configurable resolution – ADC conversion time: 0.4 µs for 12-bit resolution (2.5Msps), faster conversion times can be obtained by lowering resolution. – Self-calibration –...
Page 345: Adc Functional Description
RM0444 Analog-to-digital converter (ADC) 15.3 ADC functional description Figure 31 shows the ADC block diagram and Table 68 gives the ADC pin description. Figure 31. ADC block diagram VDD/VDDA VREF+ AREADY EOSMP ADC interrupt IRQ EOSEQ SCANDIR AUTOFF up/down Auto-off mode ADEN/ADDIS Master DATA[15:0]...
Page 346: Adc Voltage Regulator (Advregen)
Analog-to-digital converter (ADC) RM0444 Table 69. ADC internal input/output signals Internal signal Signal type Description name Analog Input Connected either to internal channels or to ADC_INi channels external channels TRGx Input ADC conversion triggers Input Internal temperature sensor output voltage SENSE Input Internal voltage reference output voltage...
Page 347: Calibration (Adcal)
RM0444 Analog-to-digital converter (ADC) If the main voltage regulator enters low-power mode (such as Low-power run mode), this buffer is disabled and the ADC cannot be used. ADC Voltage regulator enable sequence To enable the ADC voltage regulator, set ADVREGEN bit to 1 in ADC_CR register. ADC voltage regulator disable sequence To disable the ADC voltage regulator, follow the sequence below: Make sure that the ADC is disabled (ADEN = 0).
Page 348: Adc On-Off Control (Aden, Addis, Adrdy)
Analog-to-digital converter (ADC) RM0444 Figure 32. ADC calibration t CAB ADCAL ADC State Startup CALIBRATE CALIBRATION 0x00 ADC_DR[6:0] FACTOR ADC_CALFACT[6:0] by S/W by H/W MS33703V1 Calibration factor forcing Software Procedure Ensure that ADEN = 1 and ADSTART = 0 (ADC started with no conversion ongoing) Write ADC_CALFACT with the saved calibration factor The calibration factor is used as soon as a new conversion is launched.
Page 349: Figure 34. Enabling/Disabling The Adc
RM0444 Analog-to-digital converter (ADC) Follow this procedure to enable the ADC: Clear the ADRDY bit in ADC_ISR register by programming this bit to 1. Set ADEN = 1 in the ADC_CR register. Wait until ADRDY = 1 in the ADC_ISR register (ADRDY is set after the ADC startup time).
Page 350: Adc Clock (Ckmode, Presc[3:0])
Analog-to-digital converter (ADC) RM0444 15.3.5 ADC clock (CKMODE, PRESC[3:0]) The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock (ADC asynchronous clock) independent from the APB clock (PCLK). Figure 35. ADC clock scheme ADITF (Reset &...
Page 351: Table 71. Latency Between Trigger And Start Of Conversion
RM0444 Analog-to-digital converter (ADC) (1)(2) Table 71. Latency between trigger and start of conversion Latency between the trigger event ADC clock source CKMODE[1:0] and the start of conversion HSI16, SYSCLK, or Latency is not deterministic (jitter) PLLPCLK Latency is deterministic (no jitter) and equal to PCLK divided by 2 3.25 ADC clock cycles Latency is deterministic (no jitter) and equal to...
Page 352: Adc Connectivity
Analog-to-digital converter (ADC) RM0444 15.3.6 ADC connectivity ADC inputs are connected to the external channels as well as internal sources as described Figure Figure 36. ADC connectivity STM32G0xx Channel selection ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 REF+ ADC_IN7 ADC_IN8 ADC1 ADC_IN9 [10]...
Page 353: Configuring The Adc
RM0444 Analog-to-digital converter (ADC) 15.3.7 Configuring the ADC Software must write to the ADCAL and ADEN bits in the ADC_CR register if the ADC is disabled (ADEN must be 0). Software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and ADDIS = 0).
Page 354: Programmable Sampling Time (Smpx[2:0])
Analog-to-digital converter (ADC) RM0444 – Any channel can belong to in these sequences • Sequencer fully configurable The CHSELRMOD bit is set in ADC_CFGR1 register. – Sequencer length is up to 8 channels – The order in which the channels are scanned is independent from the channel number.
Page 355: Single Conversion Mode (Cont = 0)
RM0444 Analog-to-digital converter (ADC) 15.3.10 Single conversion mode (CONT In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register. Conversion is started by either: •...
Page 356: Starting Conversions (Adstart)
Analog-to-digital converter (ADC) RM0444 15.3.12 Starting conversions (ADSTART) Software starts ADC conversions by setting ADSTART = 1. When ADSTART is set, the conversion: • Starts immediately if EXTEN = 00 (software trigger) • At the next active edge of the selected hardware trigger if EXTEN ≠ 00 The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing.
Page 357: Timings
RM0444 Analog-to-digital converter (ADC) 15.3.13 Timings The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: = [1.5 + 12.5 ] x t CONV SMPL...
Page 358: Stopping An Ongoing Conversion (Adstp)
Analog-to-digital converter (ADC) RM0444 15.3.14 Stopping an ongoing conversion (ADSTP) The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the ADC_CR register. This resets the ADC operation and the ADC is idle, ready for a new operation. When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC_DR register is not updated with the current conversion).
Page 359: Discontinuous Mode (Discen)
RM0444 Analog-to-digital converter (ADC) Refer to Table 70: External triggers Section 15.3.1: ADC pins and internal signals for the list of all the external triggers that can be used for regular conversion. The software source trigger events can be generated by setting the ADSTART bit in the ADC_CR register.
Page 360: End Of Conversion, End Of Sampling Phase (Eoc, Eosmp Flags)
Analog-to-digital converter (ADC) RM0444 Table 73. t timings depending on resolution CONV SMPL (min) RES[1:0] (ns) at (ns) at CONV (ADC clock cycles) (ADC clock (ADC clock bits = 35 MHz = 35 MHz cycles) cycles) (with min. t SMPL 12.5 10.5 15.4.3...
Page 361: Example Timing Diagrams
RM0444 Analog-to-digital converter (ADC) 15.4.5 Example timing diagrams (single/continuous modes hardware/software triggers) Figure 40. Single conversions of a sequence, software trigger ADSTART SCANDIR ADC state CH17 CH17 CH10 CH10 ADC_DR by S/W by H/W MSv30338V3 1. EXTEN = 00, CONT = 0 2.
Page 362: Figure 42. Single Conversions Of A Sequence, Hardware Trigger
Analog-to-digital converter (ADC) RM0444 Figure 42. Single conversions of a sequence, hardware trigger ADSTART TRGx ADC state ADC_DR by S/W by H/W triggered ignored MSv30340V2 1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0 2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0 Figure 43.
Page 363: Low Frequency Trigger Mode
RM0444 Analog-to-digital converter (ADC) 15.4.6 Low frequency trigger mode Once the ADC is enabled or the last ADC conversion is complete, the ADC is ready to start a new conversion. The ADC needs to be started at a predefined time (t ) otherwise ADC idle converted data might be corrupted due to the transistor leakage (refer to the device...
Page 364: Figure 45. Example Of Overrun (Ovr)
Analog-to-digital converter (ADC) RM0444 When an overrun condition occurs, the ADC keeps operating and can continue to convert unless the software decides to stop and reset the sequence by setting the ADSTP bit in the ADC_CR register. The OVR flag is cleared by software by writing 1 to it. It is possible to configure if the data is preserved or overwritten when an overrun event occurs by programming the OVRMOD bit in the ADC_CFGR1 register: •...
Page 365: Managing A Sequence Of Data Converted Without Using The Dma
RM0444 Analog-to-digital converter (ADC) 15.5.3 Managing a sequence of data converted without using the DMA If the conversions are slow enough, the conversion sequence can be handled by software. In this case the software must use the EOC flag and its associated interrupt to handle each data result.
Page 366: Low-Power Features
Analog-to-digital converter (ADC) RM0444 When the DMA transfer is complete (all the transfers configured in the DMA controller have been done): • The content of the ADC data register is frozen. • Any ongoing conversion is aborted and its partial result discarded •...
Page 367: Auto-Off Mode (Autoff)
RM0444 Analog-to-digital converter (ADC) Figure 46. Wait mode conversion (continuous mode, software trigger) ADSTART ADSTP ADC_DR Read access STOP ADC state ADC_DR by H/W by S/W MSv30344V2 1. EXTEN = 00, CONT = 1 2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0 15.6.2 Auto-off mode (AUTOFF) The ADC has an automatic power management feature which is called auto-off mode, and...
Page 368: Figure 47. Behavior With Wait = 0, Autoff = 1
Analog-to-digital converter (ADC) RM0444 Figure 47. Behavior with WAIT = 0, AUTOFF = 1 TRGx ADC_DR Read access Startup Startup ADC state ADC_DR by S/W by H/W triggered MSv30345V2 1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1, AUTOFF = 1 Figure 48.
Page 369: Analog Window Watchdog (Awd1En, Awd1Sgl, Awd1Ch, Adc_Awdxcr, Adc_Awdxtr)
RM0444 Analog-to-digital converter (ADC) 15.7 Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). 15.7.1 Description of analog watchdog 1 AWD1 analog watchdog is enabled by setting the AWD1EN bit in the ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled channels (see Table 75: Analog watchdog 1 channel...
Page 370: Description Of Analog Watchdog 2 And 3
Analog-to-digital converter (ADC) RM0444 Table 75. Analog watchdog 1 channel selection Channels guarded by the analog watchdog AWD1SGL bit AWD1EN bit None All channels Single channel 1. Selected by the AWD1CH[4:0] bits 15.7.2 Description of analog watchdog 2 and 3 The second and third analog watchdogs are more flexible and can guard several selected channels by programming the AWDxCHy in ADC_AWDxCR (x = 2, 3).
Page 371: Figure 50. Adc_Awdx_Out Signal Generation
RM0444 Analog-to-digital converter (ADC) The AWD comparison is performed at the end of each ADC conversion. The ADC_AWDx_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the comparison. As ADC_AWDx_OUT is generated by the ADC_CLK domain and AWD flag is generated by the APB clock domain, the rising edges of these signals are not synchronized.
Page 372: Analog Watchdog Threshold Control
Analog-to-digital converter (ADC) RM0444 Figure 52. ADC_AWDx_OUT signal generation (on a single channel) ADC STATE Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 outside inside outside outside EOC FLAG EOS FLAG Cleared Cleared by SW by SW AWDx FLAG ADCy_AWDx_OUT - Converted channels: 1 and 2 - Only channel 1 is guarded MSv45364V1...
Page 373: Oversampler
RM0444 Analog-to-digital converter (ADC) 15.8 Oversampler The oversampling unit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted: –...
Page 374: Table 76. Maximum Output Results Vs N And M. Grayed Values Indicates Truncation
Analog-to-digital converter (ADC) RM0444 Figure 55. Numerical example with 5-bits shift and rounding Raw 20-bit data: Final result after 5-bits shift and rounding to nearest MS31929V1 Table 76 below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF.
Page 375: Adc Operating Modes Supported When Oversampling
RM0444 Analog-to-digital converter (ADC) 15.8.1 ADC operating modes supported when oversampling In oversampling mode, most of the ADC operating modes are available: • Single or continuous mode conversions, forward or backward scanned sequences and up to 8 channels programmed sequence •...
Page 376: Temperature Sensor And Internal Reference Voltage
ADC V [13] input channel. REFINT The precise voltage of V is individually measured for each part by ST during REFINT production test and stored in the system memory area. Figure 57 shows the block diagram of connections between the temperature sensor, the internal voltage reference and the ADC.
Page 377: Figure 57. Temperature Sensor And Vrefint Channel Block Diagram
RM0444 Analog-to-digital converter (ADC) Main features • Supported temperature range: –40 to 125 °C • Linearity: ±2 °C max., precision depending on calibration Figure 57. Temperature sensor and V channel block diagram REFINT TSEN control bit Temperature SENSE sensor ADC V [12] converted data VREFEN control bit...
Page 378: Battery Voltage Monitoring
Analog-to-digital converter (ADC) RM0444 Calculating the actual V voltage using the internal reference voltage REF+ voltage may be subject to variation or not precisely known. The embedded internal REF+ reference voltage (V ) and its calibration data acquired by the ADC during the REFINT manufacturing process at V can be used to evaluate the actual V...
Page 379: Adc Interrupts
RM0444 Analog-to-digital converter (ADC) the correct operation of the ADC, the V pin is internally connected to a bridge divider. This bridge is automatically enabled when VBATEN is set, to connect V to the ADC [14] input channel. As a consequence, the converted digital value is half the V voltage.
Page 380 Analog-to-digital converter (ADC) RM0444 Table 77. ADC interrupts (continued) Interrupt event Event flag Enable control bit Analog watchdog 2 status bit is set AWD2 AWD2IE Analog watchdog 3 status bit is set AWD3 AWD3IE Channel Configuration Ready CCRDY CCRDYIE End of sampling phase EOSMP EOSMPIE Overrun...
Page 381: Adc Registers
RM0444 Analog-to-digital converter (ADC) 15.12 ADC registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. 15.12.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res.
Page 382 Analog-to-digital converter (ADC) RM0444 Bit 7 AWD1: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. 0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog event occurred...
Page 383: Adc Interrupt Enable Register (Adc_Ier)
RM0444 Analog-to-digital converter (ADC) 15.12.2 ADC interrupt enable register (ADC_IER) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CCRD EOCAL AWD3I AWD2I AWD1I EOSMP ADRDY Res.
Page 384 Analog-to-digital converter (ADC) RM0444 Bit 4 OVRIE: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. 0: Overrun interrupt disabled 1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
Page 385: Adc Control Register (Adc_Cr)
RM0444 Analog-to-digital converter (ADC) 15.12.3 ADC control register (ADC_CR) Address offset: 0x08 Reset value: 0x0000 0000 ADVR ADCAL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EGEN ADSTA Res. Res. Res. Res. Res. Res. Res.
Page 386 Analog-to-digital converter (ADC) RM0444 Bit 2 ADSTART: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration).
Page 387: Adc Configuration Register 1 (Adc_Cfgr1)
RM0444 Analog-to-digital converter (ADC) 15.12.4 ADC configuration register 1 (ADC_CFGR1) Address offset: 0x0C Reset value: 0x0000 0000 AWD1E AWD1SG CHSEL Res. AWD1CH[4:0] Res. Res. Res. Res. Res. Res. DISCEN RMOD SCAND DMAC AUTOFF WAIT CONT OVRMOD EXTEN[1:0] Res. EXTSEL[2:0] ALIGN RES[1:0] DMAEN Bit 31 Reserved, must be kept at reset value.
Page 388 Analog-to-digital converter (ADC) RM0444 Bit 21 CHSELRMOD: Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: 0: Each bit of the ADC_CHSELR register enables an input 1: ADC_CHSELR register is able to sequence up to 8 channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
Page 389 RM0444 Analog-to-digital converter (ADC) Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. 00: Hardware trigger detection disabled (conversions can be started by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges...
Page 390 Analog-to-digital converter (ADC) RM0444 Bit 2 SCANDIR: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. 0: Upward scan (from CHSEL0 to CHSEL18) 1: Backward scan (from CHSEL18 to CHSEL0) Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this...
Page 391: Adc Configuration Register 2 (Adc_Cfgr2)
RM0444 Analog-to-digital converter (ADC) 15.12.5 ADC configuration register 2 (ADC_CFGR2) Address offset: 0x10 Reset value: 0x0000 0000 CKMODE[1:0] LFTRIG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TOVS OVSS[3:0] OVSR[2:0] Res.
Page 392: Adc Sampling Time Register (Adc_Smpr)
Analog-to-digital converter (ADC) RM0444 Bits 8:5 OVSS[3:0]: Oversampling shift This bit is set and cleared by software. 0000: No shift 0001: Shift 1-bit 0010: Shift 2-bits 0011: Shift 3-bits 0100: Shift 4-bits 0101: Shift 5-bits 0110: Shift 6-bits 0111: Shift 7-bits 1000: Shift 8-bits Others: Reserved Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no...
Page 393: Adc Watchdog Threshold Register (Adc_Awd1Tr)
RM0444 Analog-to-digital converter (ADC) Bits 31:27 Reserved, must be kept at reset value. Bits 26:8 SMPSEL[18:0] Channel-x sampling time selection These bits are written by software to define which sampling time is used. 0: Sampling time of CHANNELx use the setting of SMP1[2:0] register. 1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Page 394: Adc Watchdog Threshold Register (Adc_Awd2Tr)
Analog-to-digital converter (ADC) RM0444 Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 15.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR) on page 369.
Page 395: Adc Channel Selection Register [Alternate] (Adc_Chselr)
RM0444 Analog-to-digital converter (ADC) 15.12.9 ADC channel selection register [alternate] (ADC_CHSELR) Address offset: 0x28 Reset value: 0x0000 0000 The same register can be used in two different modes: – Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current section.
Page 396: Adc Channel Selection Register [Alternate] (Adc_Chselr)
Analog-to-digital converter (ADC) RM0444 15.12.10 ADC channel selection register [alternate] (ADC_CHSELR) Address offset: 0x28 Reset value: 0x0000 0000 The same register can be used in two different modes: – Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current previous section.
Page 397 RM0444 Analog-to-digital converter (ADC) Bits 19:16 SQ5[3:0]: 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
Page 398: Adc Watchdog Threshold Register (Adc_Awd3Tr)
Analog-to-digital converter (ADC) RM0444 15.12.11 ADC watchdog threshold register (ADC_AWD3TR) Address offset: 0x2C Reset value: 0x0FFF 0000 Res. Res. Res. Res. HT3[11:0] Res. Res. Res. Res. LT3[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 HT3[11:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog.
Page 399: Adc Analog Watchdog 2 Configuration Register (Adc_Awd2Cr)
RM0444 Analog-to-digital converter (ADC) 15.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR) Address offset: 0xA0 Reset value: 0x0000 0000 AWD2 AWD2 AWD2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CH18 CH17 CH16 AWD2 AWD2 AWD2 AWD2 AWD2...
Page 400: Adc Calibration Factor (Adc_Calfact)
Analog-to-digital converter (ADC) RM0444 15.12.15 ADC Calibration factor (ADC_CALFACT) Address offset: 0xB4 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 401 RM0444 Analog-to-digital converter (ADC) Bits 31:25 Reserved, must be kept at reset value. Bit 24 VBATEN: V enable This bit is set and cleared by software to enable/disable the V channel. 0: V channel disabled, DAC_OUT2 connected to ADC channel 14 1: V channel enabled Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no...
Page 402: Adc Register Map
Analog-to-digital converter (ADC) RM0444 15.13 ADC register map The following table summarizes the ADC registers. Table 78. ADC register map and reset values Offset Register ADC_ISR 0x00 Reset value ADC_IER 0x04 Reset value ADC_CR 0x08 Reset value EXTSEL ADC_CFGR1 AWDCH[4:0] [2:0] [1:0] 0x0C...
Page 403 RM0444 Analog-to-digital converter (ADC) Table 78. ADC register map and reset values (continued) Offset Register 0x30 0x34 Reserved Reserved 0x38 0x3C ADC_DR DATA[15:0] 0x40 Reset value Reserved Reserved 0xA0 ADC_AWD2CR Reset value 0xA4 ADC_AWD3CR Reset value Reserved Reserved ADC_CALFACT CALFACT[6:0] 0xB4 Reset value Reserved...
Page 404: Digital-To-Analog Converter (Dac)
Digital-to-analog converter (DAC) RM0444 Digital-to-analog converter (DAC) 16.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 405: Dac Implementation
RM0444 Digital-to-analog converter (DAC) 16.3 DAC implementation Table 79. DAC features DAC features DAC1 Dual channel Output buffer I/O connection DAC1_OUT1 on PA4, DAC1_OUT2 on PA5 Maximum sampling time 1MSPS Autonomous mode 1. There is no DAC on STM32G031xx and STM32G041xx. RM0444 Rev 5 405/1390...
Page 406: Dac Functional Description
Digital-to-analog converter (DAC) RM0444 16.4 DAC functional description 16.4.1 DAC block diagram Figure 59. Dual-channel DAC block diagram Offset calibration dac_ch1_trg1 OTRIM1[5:0] bits TRIG MODE1 bits dac_ch1_trg15 Buffer TSEL1 DOR1 [3:0] converter 1 bits dac_ch1_dma 12-bit dac_unr_it Control registers dac_pclk &...
Page 407: Dac Pins And Internal Signals
RM0444 Digital-to-analog converter (DAC) 16.4.2 DAC pins and internal signals The DAC includes: • Up to two output channels • The DAC_OUTx can be disconnected from the output pin and used as an ordinary GPIO • The dac_outx can use an internal pin connection to on-chip peripherals such as comparator, operational amplifier and ADC (if available).
Page 408: Dac Channel Enable
Digital-to-analog converter (DAC) RM0444 Table 82. DAC interconnection Signal name Source Type dac_hold_ck ck_lsi (selected in the RCC) LSI clock selected in the RCC dac_chx_trg1 (x = 1, 2) tim1_trgo Internal signal from on-chip timers dac_chx_trg2 (x = 1, 2) tim2_trgo Internal signal from on-chip timers dac_chx_trg3 (x = 1, 2)
Page 409: Figure 60. Data Registers In Single Dac Channel Mode
RM0444 Digital-to-analog converter (DAC) Figure 60. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710b • Dual DAC channels (when available) There are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) –...
Page 410: Dac Conversion
Digital-to-analog converter (DAC) RM0444 16.4.5 DAC conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write operation to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD). Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one dac_pclk clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset).
Page 411: Dma Requests
RM0444 Digital-to-analog converter (DAC) If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Note: TSELx[3:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one dac_pclk clock cycle.
Page 412: Figure 63. Dac Lfsr Register Calculation Algorithm
Digital-to-analog converter (DAC) RM0444 Figure 63. DAC LFSR register calculation algorithm ai14713c The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then transferred into the DAC_DORx register.
Page 413: Triangle-Wave Generation
RM0444 Digital-to-analog converter (DAC) 16.4.10 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to 10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three dac_pclk clock cycles after each trigger event.
Page 414: Dac Channel Modes
Digital-to-analog converter (DAC) RM0444 16.4.11 DAC channel modes Each DAC channel can be configured in Normal mode or Sample and hold mode. The output buffer can be enabled to allow a high drive capability. Before enabling output buffer, the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded after reset) and can be adjusted by software during application operation.
Page 415: Table 83. Sample And Refresh Timings
RM0444 Digital-to-analog converter (DAC) The timings for the three phases above are in units of LSI clock periods. As an example, to configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs assuming LSI ~32 KHz is selected: 12 cycles are required for sample phase: TSAMPLEx[9:0] = 11, 62 cycles are required for hold phase: THOLDx[9:0] = 62,...
Page 416: Table 84. Channel Output Modes Summary
Digital-to-analog converter (DAC) RM0444 Figure 67. DAC Sample and hold mode phase diagram Sampling phase Hold phase Sampling phase Refresh dac_hold phase MSv45340V3 Like in Normal mode, the Sample and hold mode has different configurations. To enable the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to: •...
Page 417: Dac Channel Buffer Calibration
RM0444 Digital-to-analog converter (DAC) Table 84. Channel output modes summary (continued) MODE [2:0] Mode Buffer Output connections Connected to external pin Enabled Connected to external pin and to on chip peripherals (such as comparators) Sample and hold mode Connected to external pin and to on chip peripherals (such as comparators) Disabled Connected to on chip peripherals (such as comparators)
Page 418: Dual Dac Channel Conversion Modes
Digital-to-analog converter (DAC) RM0444 If the DAC channel is active, write 0 to ENx bit in DAC_CR to disable the channel. Select a mode where the buffer is enabled, by writing to DAC_MCR register, MODEx[2:0] = 000b or 001b or 100b or 101b. Start the DAC channelx calibration, by setting the CENx bit in DAC_CR register to 1.
Page 419 RM0444 Digital-to-analog converter (DAC) When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three dac_pclk clock cycles later). When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three dac_pclk clock cycles later). Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2.
Page 420 Digital-to-analog converter (DAC) RM0444 Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2 bitfields.
Page 421 RM0444 Digital-to-analog converter (DAC) Set the two DAC channel trigger enable bits TEN1 and TEN2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1 and TSEL2 bitfields. Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).
Page 422: Dac Low-Power Modes
Digital-to-analog converter (DAC) RM0444 Set the two DAC channel trigger enable bits TEN1 and TEN2 Configure the same trigger source for both DAC channels by setting the same value in the TSEL1 and TSEL2 bitfields. Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum amplitude value using the MAMPx[3:0] bits.
Page 423: Dac Interrupts
RM0444 Digital-to-analog converter (DAC) 16.6 DAC interrupts Table 86. DAC interrupts Interrupt Interrupt Enable Interrupt clear Exit Sleep Exit Stop Exit Standby Event flag acronym event control bit method mode mode mode DMAUDRI Write DMAUDR underrun DMAUDRx = 1 RM0444 Rev 5 423/1390...
Page 424: Dac Registers
Digital-to-analog converter (DAC) RM0444 16.7 DAC registers Refer to Section 1 on page 53 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 16.7.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU DMAE...
Page 425 RM0444 Digital-to-analog converter (DAC) Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 426 Digital-to-analog converter (DAC) RM0444 Bit 16 EN2: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 0: DAC channel2 disabled 1: DAC channel2 enabled Note: These bits are available only on dual-channel DACs. Refer to Section 16.3: DAC implementation.
Page 427: Dac Software Trigger Register (Dac_Swtrgr)
RM0444 Digital-to-analog converter (DAC) Bits 5:2 TSEL1[3:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 0000: SWTRIG1 0001: dac_ch1_trg1 0010: dac_ch1_trg2 1111: dac_ch1_trg15 Refer to the trigger selection tables in Section 16.4.2: DAC pins and internal signals details on trigger configuration and mapping.
Page 428: Dac Channel1 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12R1)
Digital-to-analog converter (DAC) RM0444 Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. 0: No trigger 1: Trigger Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.
Page 429: Dac Channel1 8-Bit Right Aligned Data Holding Register (Dac_Dhr8R1)
RM0444 Digital-to-analog converter (DAC) Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1. Bits 3:0 Reserved, must be kept at reset value. 16.7.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
Page 430: Dac Channel2 12-Bit Left Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0444 16.7.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) This register is available only on dual-channel DACs. Refer to Section 16.3: DAC implementation. Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res.
Page 431: Dual Dac 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12Rd)
RM0444 Digital-to-analog converter (DAC) 16.7.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. DACC2DHR[11:0] Res. Res. Res. Res. DACC1DHR[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 432: Dual Dac 8-Bit Right Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0444 16.7.11 Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
Page 433: Dac Channel2 Data Output Register (Dac_Dor2)
RM0444 Digital-to-analog converter (DAC) 16.7.13 DAC channel2 data output register (DAC_DOR2) This register is available only on dual-channel DACs. Refer to Section 16.3: DAC implementation. Address offset: 0x30 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 434 Digital-to-analog converter (DAC) RM0444 Bit 31 BWST2: DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete.
Page 435: Dac Calibration Control Register (Dac_Ccr)
RM0444 Digital-to-analog converter (DAC) 16.7.15 DAC calibration control register (DAC_CCR) Address offset: 0x38 Reset value: 0x00XX 00XX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM2[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM1[4:0] Bits 31:21 Reserved, must be kept at reset value.
Page 436 Digital-to-analog converter (DAC) RM0444 Bits 18:16 MODE2[2:0]: DAC channel2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored.
Page 437: Dac Channel1 Sample And Hold Sample Time Register
RM0444 Digital-to-analog converter (DAC) 16.7.17 DAC channel1 sample and hold sample time register (DAC_SHSR1) Address offset: 0x40 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 438: Dac Sample And Hold Time Register (Dac_Shhr)
Digital-to-analog converter (DAC) RM0444 16.7.19 DAC sample and hold time register (DAC_SHHR) Address offset: 0x48 Reset value: 0x0001 0001 Res. Res. Res. Res. Res. Res. THOLD2[9:0] Res. Res. Res. Res. Res. Res. THOLD1[9:0] Bits 31:26 Reserved, must be kept at reset value. Bits 25:16 THOLD2[9:0]: DAC channel2 hold time (only valid in Sample and hold mode).
Page 439 RM0444 Digital-to-analog converter (DAC) Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 TREFRESH2[7:0]: DAC channel2 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs.
Page 440: Dac Register Map
Digital-to-analog converter (DAC) RM0444 16.7.21 DAC register map Table 87 summarizes the DAC registers. Table 87. DAC register map and reset values Register Offset name DAC_CR 0x00 Reset value DAC_ SWTRGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0] DHR12L1...
Page 441 RM0444 Digital-to-analog converter (DAC) Table 87. DAC register map and reset values (continued) Register Offset name DAC_CCR OTRIM2[4:0] OTRIM1[4:0] 0x38 Reset value X X X X MODE2 MODE1 DAC_MCR [2:0] [2:0] 0x3C Reset value DAC_ TSAMPLE1[9:0] SHSR1 0x40 Reset value DAC_ TSAMPLE2[9:0] SHSR2...
Page 442: Voltage Reference Buffer (Vrefbuf)
Voltage reference buffer (VREFBUF) RM0444 Voltage reference buffer (VREFBUF) 17.1 Introduction The devices embed a voltage reference buffer which can be used as voltage reference for ADC, DAC and also as voltage reference for external components through the VREF+ pin. When the VREF+ pin is double-bonded with VDDA pin in a package, the voltage reference buffer is not available and must be kept disabled (refer to datasheet for packages pinout description).
Page 443: Vrefbuf Registers
RM0444 Voltage reference buffer (VREFBUF) 17.3 VREFBUF registers 17.3.1 VREFBUF control and status register (VREFBUF_CSR) Address offset: 0x00 Reset value: 0x0000 0002 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 444: Vrefbuf Calibration Control Register (Vrefbuf_Ccr)
Voltage reference buffer (VREFBUF) RM0444 17.3.2 VREFBUF calibration control register (VREFBUF_CCR) Address offset: 0x04 Reset value: 0x0000 00XX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 445: Comparator (Comp)
RM0444 Comparator (COMP) Comparator (COMP) 18.1 Introduction The devices embed COMP1, COMP2, and COMP3 (the last on STM32G0B1xx and STM32G0C1xx only) ultra-low-power comparators. The comparators can be used for a variety of functions including: • Wakeup from low-power mode triggered by an analog signal, •...
Page 446: Comp Functional Description
Comparator (COMP) RM0444 18.3 COMP functional description 18.3.1 COMP block diagram The block diagram of the comparators is shown in Figure Figure 68. Comparator block diagram COMPx INPSEL COMPx WINMODE COMPx_INP COMPx POLARITY COMPx_INP I/Os COMPy_INP COMPx COMPx_INM COMPx INMSEL GPIO alternate function COMPx_INM I/Os...
Page 447: Table 91. Comp1 Inverting Input Assignment
RM0444 Comparator (COMP) Table 91. COMP1 inverting input assignment COMP1_INM COMP1_INMSEL[3:0] ¼ V 0000 REFINT ½ V 0001 REFINT ¾ V 0010 REFINT 0011 REFINT DAC Channel1 0100 DAC Channel2 0101 0110 0111 1000 ¼ V > 1000 REFINT Table 92. COMP2 non-inverting input assignment COMP2_INP COMP2_INPSEL[1:0] Open...
Page 448: Comp Reset And Clocks
Comparator (COMP) RM0444 Table 94. COMP3 non-inverting input assignment COMP3_INP COMP3_INPSEL[1:0] Open Table 95. COMP3 inverting input assignment COMP3_INM COMP3_INMSEL[3:0] ¼ V 0000 REFINT ½ V 0001 REFINT ¾ V 0010 REFINT 0011 REFINT DAC Channel1 0100 DAC Channel2 0101 0110 0111 1000...
Page 449: Window Comparator
RM0444 Comparator (COMP) 18.3.5 Window comparator The purpose of window comparator is to monitor the analog voltage if it is within specified voltage range defined by lower and upper threshold. COMP1 and COMP2 or COMP2 and COMP3 can combine to create a window comparator. The monitored analog voltage is connected to the non-inverting (plus) inputs of comparators connected together and the upper and lower threshold voltages are connected to the inverting (minus) inputs of the comparators.
Page 450: Comparator Output Blanking Function
Comparator (COMP) RM0444 18.3.7 Comparator output blanking function The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes).It consists of a selection of a blanking window which is a timer output compare signal.
Page 451: Comp Low-Power Modes
RM0444 Comparator (COMP) 18.4 COMP low-power modes Table 96. Comparator behavior in the low power modes Mode Description No effect on the comparators. Sleep Comparator interrupts cause the device to exit the Sleep mode. Low-power run No effect. Low-power sleep No effect. COMP interrupts cause the device to exit the Low-power sleep mode. Stop 0 No effect on the comparators.
Page 452 Comparator (COMP) RM0444 System reset value: 0x0000 0000 LOCK VALUE Res. Res. Res. Res. Res. BLANKSEL PWRMODE HYST POLARITY WINOUT Res. Res. WINMODE Res. INPSEL INMSEL Res. Res. Res. Bit 31 LOCK: COMP1_CSR register lock This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits.
Page 453: Comparator 2 Control And Status Register (Comp2_Csr)
RM0444 Comparator (COMP) Bit 11 WINMODE: Comparator 1 non-inverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP1_INP input of the comparator 1: 0: Signal selected with INPSEL[1:0] bitfield of this register 1: COMP2_INP signal of the comparator 2 (required for window mode, see Figure Bit 10 Reserved, must be kept at reset value...
Page 454 Comparator (COMP) RM0444 Bit 31 LOCK: COMP2_CSR register lock This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only. 0: Not locked 1: Locked Bit 30 VALUE: Comparator 2 output status This bit is read-only.
Page 455: Comparator 3 Control And Status Register (Comp3_Csr)
RM0444 Comparator (COMP) Bits 9:8 INPSEL[1:0]: Comparator 2 signal selector for non-inverting input This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP2_INP of the comparator 2 (also see the WINMODE bit): 00: PB4 01: PB6 10: PA3...
Page 456 Comparator (COMP) RM0444 Bit 24:20 BLANKSEL[4:0]: Comparator 3 blanking source selector This bitfield is controlled by software (if not locked). It selects the blanking source: 00000: None (no blanking) xxxx1: TIM1 OC4 xxx1x: TIM1 OC5 xx1xx: TIM2 OC3 x1xxx: TIM3 OC3 1xxxx: TIM15 OC2 Bit 19:18 PWRMODE[1:0]: Comparator 3 power mode selector This bitfield is controlled by software (if not locked).
Page 457 RM0444 Comparator (COMP) Bits 7:4 INMSEL[3:0]: Comparator 3 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP3_INM of the comparator 3: 0000: 1/4 V REFINT 0001: 1/2 V REFINT 0010: 3/4 V...
Page 458: Comp Register Map
Comparator (COMP) RM0444 18.6.4 COMP register map The following table summarizes the comparator registers. The comparator registers share SYSCFG peripheral register base addresses. Table 98. COMP register map and reset values Offset Register COMP1_CSR BLANKSEL[4:0] 0x00 Reset value COMP2_CSR BLANKSEL[4:0] 0x04 Reset value COMP3_CSR...
Page 459: True Random Number Generator (Rng)
RM0444 True random number generator (RNG) True random number generator (RNG) 19.1 Introduction The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.
Page 460: Rng Functional Description
True random number generator (RNG) RM0444 19.3 RNG functional description 19.3.1 RNG block diagram Figure 72 shows the RNG block diagram. Figure 72. RNG block diagram True RNG rng_it Conditioning logic Banked Registers RNG_CR control RNG_DR data interface RNG_SR status 128-bit Fault detection AHB clock domain...
Page 461: Random Number Generation
RM0444 True random number generator (RNG) 19.3.3 Random number generation The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. Within its boundary the RNG implements the entropy source model pictured on Figure It includes an analog noise source, a digitization stage with post-processing, a conditioning algorithm, a health monitoring block and two interfaces that are used to interact with the entropy source: GetEntropy and HealthTest.
Page 462 True random number generator (RNG) RM0444 Post processing The sample values obtained from a true random noise source consist of 2-bit bitstrings. Because this noise source output is biased, the RNG implements a post-processing component that reduces that bias to a tolerable level. More specifically, for each of the two noise source bits the RNG takes half of the bits from the sampled noise source, and half of the bits from inverted sampled noise source.
Page 463: Rng Initialization
RM0444 True random number generator (RNG) Health checks This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability. The RNG implements the following health check features. Continuous health tests, running indefinitely on the output of the noise source –...
Page 464: Rng Operation
True random number generator (RNG) RM0444 The associated initialization time can be found in Section 19.5: RNG processing time. Figure 74. RNG initialization overview Noise source enable RNGEN=0, then RNGEN=1 Conditioning hardware init Drop samples then check again Error state Generate samples Continuous test(s) not OK...
Page 465: Rng Clocking
RM0444 True random number generator (RNG) To run the RNG in polling mode following steps are recommended: Enable the random number generation by setting the RNGEN bit to “1” in the RNG_CR register. Read the RNG_SR register and check that: –...
Page 466: Rng Low-Power Usage
True random number generator (RNG) RM0444 correctly (see Section 19.3.6: RNG clocking) and then it must clear the CEIS bit interrupt flag. The CECS bit is automatically cleared when clocking condition is normal. Note: The clock error has no impact on generated random numbers, i.e. application can still read RNG_DR register.
Page 467: Rng Interrupts
RM0444 True random number generator (RNG) 19.4 RNG interrupts In the RNG an interrupt can be produced on the following events: • Data ready flag • Seed error, see Section 19.3.7: Error management • Clock error, see Section 19.3.7: Error management Dedicated interrupt enable control bits are available as shown in Table 100.
Page 468: Data Collection
True random number generator (RNG) RM0444 19.6.3 Data collection In order to run statistical tests it is required to collect samples from the entropy source at raw data level as well as at the output of the entropy source. Contact STMicroelectronics if above samples need to be retrieved for your product. 468/1390 RM0444 Rev 5...
Page 469: Rng Registers
RM0444 True random number generator (RNG) 19.7 RNG registers The RNG is associated with a control register, a data register and a status register. 19.7.1 RNG control register (RNG_CR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 470: Rng Status Register (Rng_Sr)
True random number generator (RNG) RM0444 19.7.2 RNG status register (RNG_SR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 471: Rng Data Register (Rng_Dr)
RM0444 True random number generator (RNG) 19.7.3 RNG data register (RNG_DR) Address offset: 0x008 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 216 periods of AHB clock if the output FIFO is empty.
Page 472: Rng Register Map
True random number generator (RNG) RM0444 19.7.4 RNG register map Table 101 gives the RNG register map and reset values. Table 101. RNG register map and reset map Offset Register name RNG_CR 0x000 Reset value RNG_SR 0x004 Reset value 0 0 0 RNG_DR RNDATA[31:0] 0x008...
Page 473: Aes Hardware Accelerator (Aes)
RM0444 AES hardware accelerator (AES) AES hardware accelerator (AES) 20.1 Introduction The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in Federal information processing standards (FIPS) publication 197. The peripheral supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key sizes of 128 or 256 bits.
Page 474: Aes Implementation
AES hardware accelerator (AES) RM0444 20.3 AES implementation The devices have one AES peripheral. 20.4 AES functional description 20.4.1 AES block diagram Figure 75 shows the block diagram of AES. Figure 75. AES block diagram 32-bit Banked registers access AES_KEYRx 32-bit AHB bus AES_IVRx...
Page 475: Aes Cryptographic Core
RM0444 AES hardware accelerator (AES) 20.4.3 AES cryptographic core Overview The AES cryptographic core consists of the following components: • AES core algorithm (AEA) • multiplier over a binary Galois field (GF2mul) • key input • initialization vector (IV) input •...
Page 476: Figure 76. Ecb Encryption And Decryption Principle
AES hardware accelerator (AES) RM0444 Chaining modes The following chaining modes are supported by AES, selected through the CHMOD[2:0] bitfield of the AES_CR register: • Electronic code book (ECB) • Cipher block chaining (CBC) • Counter (CTR) • Galois counter mode (GCM) •...
Page 477: Figure 77. Cbc Encryption And Decryption Principle
RM0444 AES hardware accelerator (AES) Cipher block chaining (CBC) mode Figure 77. CBC encryption and decryption principle Encryption Plaintext block 1 Plaintext block 2 Plaintext block 3 initialization vector Encrypt Encrypt Encrypt Ciphertext block 1 Ciphertext block 2 Ciphertext block 3 Decryption Plaintext block 1 Plaintext block 2...
Page 478: Figure 78. Ctr Encryption And Decryption Principle
AES hardware accelerator (AES) RM0444 Counter (CTR) mode Figure 78. CTR encryption and decryption principle Encryption Counter Counter Counter value value + 1 value + 2 Encrypt Encrypt Encrypt Plaintext block 1 Plaintext block 2 Plaintext block 3 Ciphertext block 1 Ciphertext block 2 Ciphertext block 3 Decryption...
Page 479: Figure 79. Gcm Encryption And Authentication Principle
RM0444 AES hardware accelerator (AES) Galois/counter mode (GCM) Figure 79. GCM encryption and authentication principle Initialization Counter Counter Counter vector value value + 1 value + 2 Init Encrypt Encrypt Encrypt (Encrypt) Plaintext block 1 Plaintext block 2 Plaintext block 3 Ciphertext block 1 Ciphertext block 2 Ciphertext block 3...
Page 480: Aes Procedure To Perform A Cipher Operation
AES hardware accelerator (AES) RM0444 GMAC is similar to GCM, except that it is applied on a message composed only by plaintext authenticated data (that is, only header, no payload). Counter with CBC-MAC (CCM) principle Figure 81. CCM encryption and authentication principle Count 1 Count 2 Count 3...
Page 481 RM0444 AES hardware accelerator (AES) Initialization of AES To initialize AES, first disable it by clearing the EN bit of the AES_CR register. Then perform the following steps in any order: • Configure the AES mode, by programming the MODE[1:0] bitfield of the AES_CR register.
Page 482 AES hardware accelerator (AES) RM0444 Data append using interrupt The method uses interrupt from the AES peripheral to control the data append, through the following sequence: Enable interrupts from AES by setting the CCFIE bit of the AES_CR register. Enable the AES peripheral by setting the EN bit of the AES_CR register. Write first four input data words into the AES_DINR register.
Page 483: Aes Decryption Round Key Preparation
RM0444 AES hardware accelerator (AES) 20.4.5 AES decryption round key preparation Internal key schedule is used to generate AES round keys. In AES encryption, the round 0 key is the one stored in the key registers. AES decryption must start using the last round key.
Page 484: Aes Task Suspend And Resume
AES hardware accelerator (AES) RM0444 20.4.7 AES task suspend and resume A message can be suspended if another message with a higher priority must be processed. When this highest priority message is sent, the suspended message can resume in both encryption or decryption mode.
Page 485: Figure 83. Ecb Encryption
RM0444 AES hardware accelerator (AES) Figure 83 illustrates the electronic codebook (ECB) encryption. Figure 83. ECB encryption Block 1 Block 2 AES_DINR (plaintext P1) AES_DINR (plaintext P2) Swap Swap DATATYPE[1:0] DATATYPE[1:0] management management AES_KEYRx (KEY) AES_KEYRx (KEY) Encrypt Encrypt Legend AES core Swap Swap...
Page 486: Figure 85. Cbc Encryption
AES hardware accelerator (AES) RM0444 Figure 85 illustrates the cipher block chaining (CBC) encryption. Figure 85. CBC encryption Block 1 Block 2 AES_DINR (plaintext P1) AES_DINR (plaintext P2) Swap Swap DATATYPE[1:0] DATATYPE[1:0] management management AES_IVRx (init. vector) AES_KEYRx (KEY) AES_KEYRx (KEY) Block cipher Block cipher encryption...
Page 487: Figure 87. Ecb/Cbc Encryption (Mode 1)
RM0444 AES hardware accelerator (AES) The second ciphertext block is processed in the same way as the first block, except that the I1 data from the first block is used in place of the initialization vector. The decryption continues in this way until the last complete ciphertext block is decrypted. If the message size is not a multiple of 128 bits, the final partial data block is decrypted in the way explained in Section 20.4.6: AES ciphertext stealing and data...
Page 488: Figure 88. Ecb/Cbc Decryption (Mode 3)
AES hardware accelerator (AES) RM0444 register to 000 or 001, respectively. Data type can also be defined, using DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is. Write the AES_IVRx registers with the initialization vector (required in CBC mode only). Enable AES by setting the EN bit of the AES_CR register. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in Figure Wait until the CCF flag is set in the AES_SR register.
Page 489: Aes Counter (Ctr) Mode
RM0444 AES hardware accelerator (AES) To resume the processing of a message, proceed as follows: If DMA is used, configure the DMA controller so as to complete the rest of the FIFO IN and FIFO OUT transfers. Ensure that AES is disabled (the EN bit of the AES_CR must be 0). Restore AES_CR register (with correct KEYSIZE) then restore AES_KEYRx registers.
Page 490: Figure 89. Message Construction In Ctr Mode
AES hardware accelerator (AES) RM0444 Figure 89. Message construction in CTR mode 16-byte boundaries Zero padding Ciphertext (C) 4-byte boundaries Plaintext (P) Initialization vector (IV) Counter MSv42156V1 The structure of this message is: • A 16-byte initial counter block (ICB), composed of two distinct fields: –...
Page 491: Table 103. Ctr Mode Initialization Vector Definition
RM0444 AES hardware accelerator (AES) Figure 91. CTR decryption Block 1 Block 2 AES_IVRx AES_IVRx Nonce + 32-bit counter Nonce + 32-bit counter (+1) Counter increment (+1) AES_KEYRx (KEY) AES_KEYRx (KEY) Encrypt Encrypt AES_DINR (ciphertext C1) AES_DINR (ciphertext C2) DATATYPE[1:0] DATATYPE[1:0] Swap Swap...
Page 492: Aes Galois/Counter Mode (Gcm)
AES hardware accelerator (AES) RM0444 Suspend/resume operations in CTR mode Like for the CBC mode, it is possible to interrupt a message to send a higher priority message, and resume the message that was interrupted. Detailed CBC suspend/resume sequence is described in Section 20.4.8: AES basic chaining modes (ECB, CBC).
Page 493: Table 104. Gcm Last Block Definition
RM0444 AES hardware accelerator (AES) The message has the following structure: • 16-byte initial counter block (ICB), composed of two distinct fields: – Initialization vector (IV): a 96-bit value that must be unique for each encryption cycle with a given key. Note that the GCM standard supports IVs with less than 96 bits, but in this case strict rules apply.
Page 494: Table 105. Gcm Mode Ivi Bitfield Initialization
AES hardware accelerator (AES) RM0444 GCM processing Figure 93 describes the GCM implementation in the AES peripheral. The GCM is selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register. Figure 93. GCM authenticated encryption (3) Payload Block 1 Block n AES_IVRx ICB + (32-bit counter = 0x02)
Page 495 RM0444 AES hardware accelerator (AES) The authentication mechanism in GCM mode is based on a hash function called GF2mul that performs multiplication by a fixed parameter, called hash subkey (H), within a binary Galois field. A GCM message is processed through the following phases, further described in next subsections: •...
Page 496 AES hardware accelerator (AES) RM0444 GCM payload phase This phase, identical for encryption and decryption, is executed after the GCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is: Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register.
Page 497: Aes Galois Message Authentication Code (Gmac)
RM0444 AES hardware accelerator (AES) Suspend/resume operations in GCM mode To suspend the processing of a message, proceed as follows: If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register. If DMA is not used, make sure that the current computation is completed, which is indicated by the CCF flag of the AES_SR register set to 1.
Page 498: Figure 94. Message Construction In Gmac Mode
AES hardware accelerator (AES) RM0444 A typical message construction for GMAC is given in Figure Figure 94. Message construction in GMAC mode [Len(A)] Len(A) 16-byte boundaries Last Authenticated data block 4-byte boundaries Authentication tag (T) Initialization vector (IV) Counter Zero padding MSv42158V2 AES GMAC processing Figure 95...
Page 499: Aes Counter With Cbc-Mac (Ccm)
RM0444 AES hardware accelerator (AES) 20.4.12 AES counter with CBC-MAC (CCM) Overview The AES counter with cipher block chaining-message authentication code (CCM) algorithm allows encryption and authentication of plaintext, generating the corresponding ciphertext and tag (also known as message authentication code). To ensure confidentiality, the CCM algorithm is based on AES in counter mode.
Page 500 AES hardware accelerator (AES) RM0444 standard also states that, on MSB bits of the first message block (B1), the associated data length expressed in bytes (a) must be encoded as follows: – If 0 < a < 2 , then it is encoded as [a] , that is, on two bytes.
Page 501: Table 106. Initialization Of Aes_Ivrx Registers In Ccm Mode
RM0444 AES hardware accelerator (AES) CCM processing Figure 97 describes the CCM implementation within the AES peripheral (encryption example). This mode is selected by writing 100 into the CHMOD[2:0] bitfield of the AES_CR register. Figure 97. CCM mode authenticated encryption Block 1 Block m (3) Payload...
Page 502 AES hardware accelerator (AES) RM0444 Note: In this mode, the settings 01 and 11 of the MODE[1:0] bitfield are forbidden. A CCM message is processed through the following phases, further described in next subsections: • Init phase: AES processes the first block and prepares the first counter block. •...
Page 503 RM0444 AES hardware accelerator (AES) CCM payload phase (encryption or decryption) This phase, identical for encryption and decryption, is executed after the CCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is: Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register.
Page 504 AES hardware accelerator (AES) RM0444 Suspend/resume operations in CCM mode To suspend the processing of a message in header or payload phase, proceed as follows: If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register.
Page 505: Aes Data Registers And Data Swapping
RM0444 AES hardware accelerator (AES) 20.4.13 AES data registers and data swapping Data input and output A 128-bit data block is entered into the AES peripheral with four successive 32-bit word writes into the AES_DINR register (bitfield DIN[31:0]), the most significant word (bits [127:96]) first, the least significant word (bits [31:0]) last.
Page 506: Figure 98. 128-Bit Block Construction With Respect To Data Swap
AES hardware accelerator (AES) RM0444 Figure 98. 128-bit block construction with respect to data swap increasing memory address byte 3 byte 2 byte 1 byte 0 DATATYPE[1:0] = 00: no swapping Word 3 Word 2 Word 1 Word 0 D127 D127 DATATYPE[1:0] = 01: 16-bit (half-word) swapping Word 3...
Page 507: Aes Key Registers
RM0444 AES hardware accelerator (AES) 20.4.14 AES key registers The AES_KEYRx write-only registers store the encryption or decryption key bitfield KEY[127:0] or KEY[255:0]. The data to write to each register is organized in the memory in little-endian order, that is, with most significant byte on the highest address (reads are not allowed for security reason).
Page 508: Figure 99. Dma Transfer Of A 128-Bit Data Block During Input Phase
AES hardware accelerator (AES) RM0444 DMA transfer must not include the last block. For details, refer to Section 20.4.4: AES procedure to perform a cipher operation. Figure 99. DMA transfer of a 128-bit data block during input phase Chronological order Increasing address Memory accessed through DMA Word3...
Page 509: Aes Error Management
RM0444 AES hardware accelerator (AES) When the data transferring between AES and memory is managed by DMA, the CCF flag is not relevant and can be ignored (left set) by software. It must only be cleared when transiting back to data transferring managed by software. See Suspend/resume operations in ECB/CBC modes Section 20.4.8: AES basic chaining modes (ECB, CBC)
Page 510: Aes Processing Latency
AES hardware accelerator (AES) RM0444 Table 108. AES interrupt requests Interrupt Interrupt clear AES interrupt event Event flag Enable bit acronym method computation completed flag CCFIE set CCFC read error flag RDERR ERRIE set ERRC write error flag WRERR 1. Bit of the AES_CR register. 20.6 AES processing latency The tables below summarize the latency to process a 128-bit block for each mode of...
Page 511: Aes Registers
RM0444 AES hardware accelerator (AES) 20.7 AES registers 20.7.1 AES control register (AES_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. NPBLB[3:0] Res. Res. Res. GCMPH[1:0] ERRIE CCFIE ERRC CCFC CHMOD[1:0] MODE[1:0] DATATYPE[1:0] Bits 31:24 Reserved, must be kept at reset value.
Page 512 AES hardware accelerator (AES) RM0444 Bit 12 DMAOUTEN: DMA output enable This bit enables/disables data transferring with DMA, in the output phase: 0: Disable 1: Enable When the bit is set, DMA requests are automatically generated by AES during the output data phase.
Page 513: Aes Status Register (Aes_Sr)
RM0444 AES hardware accelerator (AES) Bits 4:3 MODE[1:0]: AES operating mode This bitfield selects the AES operating mode: 00: Mode 1: encryption 01: Mode 2: key derivation (or key preparation for ECB/CBC decryption) 10: Mode 3: decryption 11: Mode 4: key derivation then single decryption Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.
Page 514: Aes Data Input Register (Aes_Dinr)
AES hardware accelerator (AES) RM0444 Bit 2 WRERR: Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): 0: Not detected 1: Detected The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register.
Page 515: Aes Data Output Register (Aes_Doutr)
RM0444 AES hardware accelerator (AES) Bits 31:0 DIN[31:0]: Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0].
Page 516: Aes Key Register 0 (Aes_Keyr0)
AES hardware accelerator (AES) RM0444 20.7.5 AES key register 0 (AES_KEYR0) Address offset: 0x10 Reset value: 0x0000 0000 KEY[31:16] KEY[15:0] Bits 31:0 KEY[31:0]: Cryptographic key, bits [31:0] This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key.
Page 517: Aes Key Register 2 (Aes_Keyr2)
RM0444 AES hardware accelerator (AES) 20.7.7 AES key register 2 (AES_KEYR2) Address offset: 0x18 Reset value: 0x0000 0000 KEY[95:80] KEY[79:64] Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. 20.7.8 AES key register 3 (AES_KEYR3) Address offset: 0x1C Reset value: 0x0000 0000 KEY[127:112]...
Page 518: Aes Initialization Vector Register 1 (Aes_Ivr1)
AES hardware accelerator (AES) RM0444 Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0] Refer to Section 20.4.15: AES initialization vector registers on page 507 for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The AES_IVRx registers may be written only when the AES peripheral is disabled 20.7.10 AES initialization vector register 1 (AES_IVR1)
Page 519: Aes Key Register 4 (Aes_Keyr4)
RM0444 AES hardware accelerator (AES) Bits 31:0 IVI[127:96]: Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. 20.7.13 AES key register 4 (AES_KEYR4) Address offset: 0x30 Reset value: 0x0000 0000 KEY[159:144] KEY[143:128] Bits 31:0 KEY[159:128]: Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
Page 520: Aes Key Register 7 (Aes_Keyr7)
AES hardware accelerator (AES) RM0444 20.7.16 AES key register 7 (AES_KEYR7) Address offset: 0x3C Reset value: 0x0000 0000 KEY[255:240] KEY[239:224] Bits 31:0 KEY[255:224]: Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. Note: The key registers from 4 to 7 are used only when the key length of 256 bits is selected. They have no effect when the key length of 128 bits is selected (only key registers 0 to 3 are used in that case).
Page 521: Aes Register Map
RM0444 AES hardware accelerator (AES) 20.7.18 AES register map Table 111. AES register map and reset values Offset Register AES_CR 0x000 Reset value AES_SR 0x004 Reset value AES_DINR DIN[31:0] 0x008 Reset value AES_DOUTR DOUT[31:0] 0x00C Reset value AES_KEYR0 KEY[31:0] 0x010 Reset value AES_KEYR1 KEY[63:32]...
Page 522 AES hardware accelerator (AES) RM0444 Table 111. AES register map and reset values (continued) Offset Register AES_KEYR7 KEY[255:224] 0x03C Reset value AES_SUSP0R SUSP[31:0] 0x040 Reset value AES_SUSP1R SUSP[31:0] 0x044 Reset value AES_SUSP2R SUSP[31:0] 0x048 Reset value AES_SUSP3R SUSP[31:0] 0x04C Reset value AES_SUSP4R SUSP[31:0] 0x050...
Page 523: Advanced-Control Timer (Tim1)
RM0444 Advanced-control timer (TIM1) Advanced-control timer (TIM1) In this section, “TIMx” should be understood as “TIM1” since there is only one instance of this type of timer for the products to which this reference manual applies. 21.1 TIM1 introduction The advanced-control timer (TIM1) consists of a 16-bit auto-reload counter driven by a programmable prescaler.
Page 524: Tim1 Main Features
Advanced-control timer (TIM1) RM0444 21.2 TIM1 main features TIM1 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. •...
Page 525: Figure 101. Advanced-Control Timer Block Diagram
RM0444 Advanced-control timer (TIM1) Figure 101. Advanced-control timer block diagram Internal clock (CK_INT) from RCC Trigger ETRF TRGO controller ETRP TIMx_ETR to other timers Polarity selection & Input to peripherals edgedetector & prescaler filter On-chip ETR ITR[0..15] sources Slave Reset, enable, up/down, count TRGI controller mode...
Page 526: Tim1 Functional Description
Advanced-control timer (TIM1) RM0444 21.3 TIM1 functional description 21.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 527: Figure 102. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0444 Advanced-control timer (TIM1) Figure 102. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 103.
Page 528: Counter Modes
Advanced-control timer (TIM1) RM0444 21.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 529: Figure 104. Counter Timing Diagram, Internal Clock Divided By 1
RM0444 Advanced-control timer (TIM1) Figure 104. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT 34 35 36 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31078V2 Figure 105. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 530: Figure 106. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timer (TIM1) RM0444 Figure 106. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31080V2 Figure 107. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 531: Figure 108. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
RM0444 Advanced-control timer (TIM1) Figure 108. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 109.
Page 532 Advanced-control timer (TIM1) RM0444 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 533: Figure 110. Counter Timing Diagram, Internal Clock Divided By 1
RM0444 Advanced-control timer (TIM1) Figure 110. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT 03 02 01 00 34 33 32 Counter register Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) MS31184V1 Figure 111. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 534: Figure 112. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timer (TIM1) RM0444 Figure 112. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 113. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 535: Figure 114. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
RM0444 Advanced-control timer (TIM1) Figure 114. Counter timing diagram, update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the...
Page 536: Figure 115. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timer (TIM1) RM0444 DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 537: Figure 116. Counter Timing Diagram, Internal Clock Divided By 2
RM0444 Advanced-control timer (TIM1) Figure 116. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0001 0000 0001 0002 0003 0003 0002 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31190V1 Figure 117. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 538: Figure 118. Counter Timing Diagram, Internal Clock Divided By N
Advanced-control timer (TIM1) RM0444 Figure 118. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31192V1 Figure 119. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02...
Page 539: Repetition Counter
RM0444 Advanced-control timer (TIM1) Figure 120. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register F8 F9 FA FB FC 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active...
Page 540: Figure 121. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
Advanced-control timer (TIM1) RM0444 In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the underflow.
Page 541: External Trigger Input
RM0444 Advanced-control timer (TIM1) 21.3.4 External trigger input The timer features an external trigger input ETR. It can be used as: • external clock (external clock mode 2, see Section 21.3.5) • trigger for the slave mode (see Section 21.3.26) •...
Page 542: Clock Selection
Advanced-control timer (TIM1) RM0444 21.3.5 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Encoder mode Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed...
Page 543: Figure 125. Ti2 External Clock Connection Example
RM0444 Advanced-control timer (TIM1) Figure 125. TI2 external clock connection example TIMx_SMCR TS[4:0] TI2F TI1F Encoder mode ITRx 000xx TIMx_CH2 TI1_ED TRGI External clock 00100 mode 1 CK_PSC TI1FP1 TI2[0] 00101 TI2F_Rising Edge External clock TI2FP2 ETRF 00110 Filter TI2[1..15] detector mode 2 ETRF...
Page 544: Figure 126. Control Circuit In External Clock Mode 1
Advanced-control timer (TIM1) RM0444 Figure 126. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR.
Page 545: Figure 128. Control Circuit In External Clock Mode 2
RM0444 Advanced-control timer (TIM1) As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 546: Capture/Compare Channels
Advanced-control timer (TIM1) RM0444 21.3.6 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control). Figure 129 Figure 132 give an overview of one Capture/Compare channel.
Page 547: Figure 131. Output Stage Of Capture/Compare Channel (Channel 1, Idem Ch. 2 And 3)
RM0444 Advanced-control timer (TIM1) Figure 131. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) TIMx_SMCR OCCS OCREF_CLR To the master mode controller ETRF Output enable ‘0’ circuit ocref_clr_int OC1REF OC1REFC OC1_DT CC1P CNT>CCR1 Output Output Dead-time TIM1_CCER mode CNT=CCR1...
Page 548: Input Capture Mode
Advanced-control timer (TIM1) RM0444 Figure 133. Output stage of capture/compare channel (channel 5, idem ch. 6) TIMx_SMCR OCCS To the master OCREF_CLR mode controller ETRF ocref_clr_int ‘0’ Output CNT > CCR5 Output enable OC5REF mode circuit CNT = CCR5 controller CC5E CC5P CC5E TIM1_CCER...
Page 549: Pwm Input Mode
RM0444 Advanced-control timer (TIM1) detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
Page 550: Forced Output Mode
Advanced-control timer (TIM1) RM0444 Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’...
Page 551: Output Compare Mode
RM0444 Advanced-control timer (TIM1) 21.3.10 Output compare mode This function is used to control an output waveform or indicate when a period of time has elapsed. Channels 1 to 4 can be output, while Channel 5 and 6 are only available inside the device (for instance, for compound waveform generation or for ADC triggering).
Page 552: Pwm Mode
Advanced-control timer (TIM1) RM0444 Figure 135. Output compare mode, toggle on OC1 Write B201h in the CC1R register 0039 003A 003B B200 B201 TIM1_CNT B201 003A TIM1_CCR1 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V1 21.3.11 PWM mode Pulse Width Modulation mode allows a signal to be generated with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 553: Figure 136. Edge-Aligned Pwm Waveforms (Arr=8)
RM0444 Advanced-control timer (TIM1) PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 528. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 554: Figure 137. Center-Aligned Pwm Waveforms (Arr=8)
Advanced-control timer (TIM1) RM0444 TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 535. Figure 137 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, •...
Page 555: Asymmetric Pwm Mode
RM0444 Advanced-control timer (TIM1) in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 556: Combined Pwm Mode
Advanced-control timer (TIM1) RM0444 Figure 138. Generation of 2 phase-shifted PWM signals with 50% duty cycle Counter register OC1REFC CCR1=0 CCR2=8 OC3REFC CCR3=3 CCR4=5 MS33117V1 21.3.13 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses.
Page 557: Combined 3-Phase Pwm Mode
RM0444 Advanced-control timer (TIM1) Figure 139. Combined PWM mode on channel 1 and 3 OC2’ OC1’ OC1REF OC2REF OC1REF’ OC2REF’ OC1REFC OC1REFC’ OC1REFC = OC1REF AND OC2REF OC1REFC’ = OC1REF’ OR OC2REF’ MS31094V1 21.3.14 Combined 3-phase PWM mode Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses.
Page 558: Complementary Outputs And Dead-Time Insertion
Advanced-control timer (TIM1) RM0444 Figure 140. 3-phase combined PWM signals with multiple trigger pulses per period Counter OC5ref OC1refC OC2refC OC3refC Preload Active OC4ref OC6ref TRGO2 MS33102V1 The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals.
Page 559: Figure 141. Complementary Output With Dead-Time Insertion
RM0444 Advanced-control timer (TIM1) Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: •...
Page 560: Using The Break Function
Advanced-control timer (TIM1) RM0444 Figure 143. Dead-time waveforms with delay greater than the positive pulse OCxREF OCxN delay MS31097V1 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 21.4.20: TIM1 break and dead-time register (TIM1_BDTR) for delay calculation.
Page 561 RM0444 Advanced-control timer (TIM1) The output enable signal and output levels during break are depending on several control bits: – the MOE bit in TIMx_BDTR register allows the outputs to be enabled/disabled by software and is reset in case of break or break2 event. –...
Page 562: Figure 144. Break And Break2 Circuitry Overview
Advanced-control timer (TIM1) RM0444 All sources are ORed before entering the timer BRK or BRK2 inputs, as per Figure 144 below. Figure 144. Break and Break2 circuitry overview Lockup LOCK Core Lockup PVD LOCK System break requests SBIF flag Parity LOCK RAM parity Error ECC LOCK Double ECC Error...
Page 563 RM0444 Advanced-control timer (TIM1) When one of the breaks occurs (selected level on one of the break inputs): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature is enabled even if the MCU oscillator is off.
Page 564: Figure 145. Various Output Behavior In Response To A Break Event On Brk (Ossi = 1)
Advanced-control timer (TIM1) RM0444 Figure 145. Various output behavior in response to a break event on BRK (OSSI = 1) BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay...
Page 565: Table 112. Behavior Of Timer Outputs Versus Brk/Brk2 Inputs
RM0444 Advanced-control timer (TIM1) The two break inputs have different behaviors on timer outputs: – The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state. – BRK2 can only disable (inactive state) the PWM outputs. The BRK has a higher priority than BRK2 input, as described in Table 112.
Page 566: Bidirectional Break Inputs
Advanced-control timer (TIM1) RM0444 Figure 147. PWM output state following BRK assertion (OSSI=0) I/O state defined by the GPIO controller (HI-Z) Deadtime I/O state I/O state defined by the GPIO controller (HI-Z) Active Inactive Disabled MS34107V1 21.3.17 Bidirectional break inputs The TIM1 are featuring bidirectional break I/Os, as represented on Figure 148.
Page 567: Table 113. Break Protection Disarming Conditions
RM0444 Advanced-control timer (TIM1) Table 113. Break protection disarming conditions BKDIR BKDSRM Break protection state (BK2DIR) (BK2DSRM) Armed Armed Disarmed Armed Arming and re-arming break circuitry The break circuitry (in input or bidirectional mode) is armed by default (peripheral reset configuration).
Page 568: Clearing The Ocxref Signal On An External Event
Advanced-control timer (TIM1) RM0444 21.3.18 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF remains low until the next update event (UEV) occurs.
Page 569: 6-Step Pwm Generation
RM0444 Advanced-control timer (TIM1) 21.3.19 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus one can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 570: One-Pulse Mode
Advanced-control timer (TIM1) RM0444 21.3.20 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 571: Retriggerable One Pulse Mode
RM0444 Advanced-control timer (TIM1) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 572: Encoder Interface Mode
Advanced-control timer (TIM1) RM0444 Figure 152. Retriggerable one pulse mode TRGI Counter Output MS33106V1 21.3.22 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’...
Page 573: Table 114. Counting Direction Versus Encoder Signals
RM0444 Advanced-control timer (TIM1) Table 114. Counting direction versus encoder signals Level on TI1FP1 signal TI2FP2 signal opposite signal (TI1FP1 Active edge for TI2, Rising Falling Rising Falling TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 574: Uif Bit Remapping
Advanced-control timer (TIM1) RM0444 Figure 154 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 154. Example of encoder interface mode with TI1FP1 polarity inverted. forward jitter backward jitter forward Counter down down MS33108V1...
Page 575: Timer Input Xor Function
RM0444 Advanced-control timer (TIM1) 21.3.24 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 576 Advanced-control timer (TIM1) RM0444 Example: one wants to change the PWM configuration of the advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, •...
Page 577: Figure 156. Example Of Hall Sensor Interface
RM0444 Advanced-control timer (TIM1) Figure 156. Example of Hall sensor interface TIH1 TIH2 TIH3 Counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step MS32672V1 RM0444 Rev 5 577/1390...
Page 578: Timer Synchronization
Advanced-control timer (TIM1) RM0444 21.3.26 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. Refer to Section 22.3.19: Timer synchronization for details. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Page 579: Figure 158. Control Circuit In Gated Mode
RM0444 Advanced-control timer (TIM1) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 580: Figure 159. Control Circuit In Trigger Mode
Advanced-control timer (TIM1) RM0444 register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=00110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 581: Figure 160. Control Circuit In External Clock Mode 2 + Trigger Mode
RM0444 Advanced-control timer (TIM1) In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: –...
Page 582: Adc Synchronization
Advanced-control timer (TIM1) RM0444 21.3.27 ADC synchronization The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as: –...
Page 583: Debug Mode
RM0444 Advanced-control timer (TIM1) This is done in the following steps: Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.
Page 584: Tim1 Registers
Advanced-control timer (TIM1) RM0444 21.4 TIM1 registers Refer to for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 21.4.1 TIM1 control register 1 (TIM1_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE Res.
Page 585: Tim1 Control Register 2 (Tim1_Cr2)
RM0444 Advanced-control timer (TIM1) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source...
Page 586 Advanced-control timer (TIM1) RM0444 Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: 0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2).
Page 587 RM0444 Advanced-control timer (TIM1) Bit 12 OIS3: Output Idle state 3 (OC3 output) Refer to OIS1 bit Bit 11 OIS2N: Output Idle state 2 (OC2N output) Refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) Refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0...
Page 588: Tim1 Slave Mode Control Register (Tim1_Smcr)
Advanced-control timer (TIM1) RM0444 Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 589 RM0444 Advanced-control timer (TIM1) Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of f frequency. A CK_INT prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
Page 590: Tim1 Dma/Interrupt Enable Register (Tim1_Dier)
Advanced-control timer (TIM1) RM0444 Bit 3 OCCS: OCREF clear selection This bit is used to select the OCREF clear source. 0: OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIM1_OR1.OCREF_CLR 1: OCREF_CLR_INT is connected to ETRF Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 591 RM0444 Advanced-control timer (TIM1) Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled...
Page 592: Tim1 Status Register (Tim1_Sr)
Advanced-control timer (TIM1) RM0444 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 21.4.5...
Page 593 RM0444 Advanced-control timer (TIM1) Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 B2IF: Break 2 interrupt flag...
Page 594: Tim1 Event Generation Register (Tim1_Egr)
Advanced-control timer (TIM1) RM0444 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 595: Tim1 Capture/Compare Mode Register 1 [Alternate]
RM0444 Advanced-control timer (TIM1) Bit 2 CC2G: Capture/Compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 596: Tim1 Capture/Compare Mode Register 1 [Alternate]
Advanced-control timer (TIM1) RM0444 Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC.
Page 597 RM0444 Advanced-control timer (TIM1) corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Output compare mode: Res.
Page 598 Advanced-control timer (TIM1) RM0444 Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 599: Tim1 Capture/Compare Mode Register 2 [Alternate]
RM0444 Advanced-control timer (TIM1) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 600: Tim1 Capture/Compare Mode Register 2 [Alternate]
Advanced-control timer (TIM1) RM0444 Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 IC4F[3:0]: Input capture 4 filter Refer to IC1F[3:0] description. Bits 11:10 IC4PSC[1:0]: Input capture 4 prescaler Refer to IC1PSC[1:0] description. Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 601 RM0444 Advanced-control timer (TIM1) Bits 31:25 Reserved, must be kept at reset value. Bits 23:17 Reserved, must be kept at reset value. Bit 15 OC4CE: Output compare 4 clear enable Refer to OC1CE description. Bits 24, 14:12 OC4M[3:0]: Output compare 4 mode Refer to OC3M[3:0] description.
Page 602: Tim1 Capture/Compare Enable Register
Advanced-control timer (TIM1) RM0444 21.4.11 TIM1 capture/compare enable register (TIM1_CCER) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC6P CC6E Res. Res. CC5P CC5E CC4NP Res. CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P...
Page 603 RM0444 Advanced-control timer (TIM1) Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low.
Page 604: Table 116. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
Advanced-control timer (TIM1) RM0444 Bit 0 CC1E: Capture/Compare 1 output enable 0: Capture mode disabled / OC1 is not active (see below) 1: Capture mode enabled / OC1 signal is output on the corresponding output pin When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state.
Page 605: Tim1 Counter (Tim1_Cnt)
RM0444 Advanced-control timer (TIM1) 21.4.12 TIM1 counter (TIM1_CNT) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Page 606: Tim1 Repetition Counter Register (Tim1_Rcr)
Advanced-control timer (TIM1) RM0444 21.4.15 TIM1 repetition counter register (TIM1_RCR) Address offset: 0x30 Reset value: 0x0000 REP[15:0] Bits 15:0 REP[15:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 607: Tim1 Capture/Compare Register 2 (Tim1_Ccr2)
RM0444 Advanced-control timer (TIM1) 21.4.17 TIM1 capture/compare register 2 (TIM1_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
Page 608: Tim1 Capture/Compare Register 4 (Tim1_Ccr4)
Advanced-control timer (TIM1) RM0444 21.4.19 TIM1 capture/compare register 4 (TIM1_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE).
Page 609 RM0444 Advanced-control timer (TIM1) Bit 28 BKBID: Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode.
Page 610 Advanced-control timer (TIM1) RM0444 Bits 23:20 BK2F[3:0]: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: f...
Page 611 RM0444 Advanced-control timer (TIM1) Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
Page 612: Tim1 Dma Control Register (Tim1_Dcr)
Advanced-control timer (TIM1) RM0444 Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 21.4.11: TIM1 capture/compare enable register (TIM1_CCER)).
Page 613: Tim1 Dma Address For Full Transfer
RM0444 Advanced-control timer (TIM1) Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers.
Page 614: Tim1 Option Register 1 (Tim1_Or1)
Advanced-control timer (TIM1) RM0444 Bits 31:0 DMAB[31:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 615: Tim1 Capture/Compare Register 5 (Tim1_Ccr5)
RM0444 Advanced-control timer (TIM1) Bits 31:25 Reserved, must be kept at reset value. Bits 23:17 Reserved, must be kept at reset value. Bit 15 OC6CE: Output compare 6 clear enable Refer to OC1CE description. Bits 24, 14, 13, 12 OC6M[3:0]: Output compare 6 mode Refer to OC1M description.
Page 616: Tim1 Capture/Compare Register 6 (Tim1_Ccr6)
Advanced-control timer (TIM1) RM0444 Bit 31 GC5C3: Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2).
Page 617: Tim1 Alternate Function Option Register 1 (Tim1_Af1)
RM0444 Advanced-control timer (TIM1) 21.4.27 TIM1 alternate function option register 1 (TIM1_AF1) Address offset: 0x60 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2] ETRSEL[1:0] Res. BKINP Res. Res. Res. Res.
Page 618 Advanced-control timer (TIM1) RM0444 Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input polarity is not inverted (active low if BKP=0, active high if BKP=1) 1: COMP1 input polarity is inverted (active high if BKP=0, active low if BKP=1) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 619: Tim1 Alternate Function Register 2 (Tim1_Af2)
RM0444 Advanced-control timer (TIM1) 21.4.28 TIM1 Alternate function register 2 (TIM1_AF2) Address offset: 0x64 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CMP3 CMP2 CMP1 Res.
Page 620: Tim1 Timer Input Selection Register (Tim1_Tisel)
Advanced-control timer (TIM1) RM0444 Bit 3 BK2CMP3E: BRK2 COMP3 enable This bit enables the COMP3 for the timer’s BRK2 input. COMP3 output is ‘ORed’ with the other BRK2 sources. 0: COMP3 input disabled 1: COMP3 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 621 RM0444 Advanced-control timer (TIM1) Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 TI3SEL[3:0]: selects TI3[0] to TI3[15] input 0000: TIM1_CH3 input 0001: COMP3 output (available on STM32G0B1xx and STM32G0C1xx salestypes only) Others: Reserved Bits 15:12 Reserved, must be kept at reset value. Bits 11:8 TI2SEL[3:0]: selects TI2[0] to TI2[15] input 0000: TIM1_CH2 input 0001: COMP2 output...
Page 622: Tim1 Register Map
Advanced-control timer (TIM1) RM0444 21.4.30 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: Table 117. TIM1 register map and reset values Register Offset name TIM1_CR1 [1:0] [1:0] 0x00 Reset value TIM1_CR2 MMS2[3:0] [2:0] 0x04...
Page 623 RM0444 Advanced-control timer (TIM1) Table 117. TIM1 register map and reset values (continued) Register Offset name TIM1_CNT CNT[15:0] 0x24 Reset value TIM1_PSC PSC[15:0] 0x28 Reset value TIM1_ARR ARR[15:0] 0x2C Reset value TIM1_RCR REP[15:0] 0x30 Reset value TIM1_CCR1 CCR1[15:0] 0x34 Reset value TIM1_CCR2 CCR2[15:0] 0x38...
Page 624 Advanced-control timer (TIM1) RM0444 Table 117. TIM1 register map and reset values (continued) Register Offset name TIM1_CCR5 CCR5[15:0] 0x58 Reset value TIM1_CCR6 CCR6[15:0] 0x5C Reset value TIM1_AF1 ETRSEL 0x60 [3:0] Reset value TIM1_AF2 0x64 Reset value TIM1_TISEL TI4SEL[3:0] TI3SEL[3:0] TI2SEL[3:0] TI1SEL[3:0] 0x68 Reset value...
Page 625: General-Purpose Timers (Tim2/Tim3/Tim4)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) General-purpose timers (TIM2/TIM3/TIM4) 22.1 TIM2/TIM3/TIM4 introduction The general-purpose timers consist of a 16-bit/32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 626: Figure 161. General-Purpose Timer Block Diagram
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 161. General-purpose timer block diagram Internal clock (CK_INT) From RCC Trigger ETRF controller TIMx_ETR TRGO Polarity selection & edge ETRP Input filter detector & prescaler to other timers to peripherals On-chip ETR ITR[0..15] sources Slave TRGI Reset, enable, count controller...
Page 627: Tim2/Tim3/Tim4 Functional Description
RM0444 General-purpose timers (TIM2/TIM3/TIM4) 22.3 TIM2/TIM3/TIM4 functional description 22.3.1 Time-base unit The main block of the programmable timer is a 16-bit/32-bit counter with its related auto- reload register. The counter can count up, down or both up and down but also down or both up and down.
Page 628: Figure 162. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 162. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 163.
Page 629: Counter Modes
RM0444 General-purpose timers (TIM2/TIM3/TIM4) 22.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 630: Figure 165. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 165. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0035 0036 0000 0001 0002 0003 0034 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 166. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 631: Figure 167. Counter Timing Diagram, Internal Clock Divided By N
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Figure 167. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 168. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 632: Figure 169. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 169. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 633: Figure 170. Counter Timing Diagram, Internal Clock Divided By 1
RM0444 General-purpose timers (TIM2/TIM3/TIM4) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 170. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 01 00 34 33 32 Counter underflow (cnt_udf) Update event (UEV)
Page 634: Figure 172. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 172. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 173. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 635: Figure 174. Counter Timing Diagram, Update Event When Repetition Counter
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Figure 174. Counter timing diagram, Update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the...
Page 636: Figure 175. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
General-purpose timers (TIM2/TIM3/TIM4) RM0444 DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 637: Figure 176. Counter Timing Diagram, Internal Clock Divided By 2
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Figure 176. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0002 0001 0000 0001 0002 0003 0003 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31190V1 Figure 177. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 638: Figure 178. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 178. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31192V1 Figure 179. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02...
Page 639: Clock Selection
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Figure 180. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register 31 30 2F F8 F9 FA FB FC Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active...
Page 640: Figure 181. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 181. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register.
Page 641: Figure 183. Control Circuit In External Clock Mode 1
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Note: The capture prescaler is not used for triggering, so it does not need to be configured. Select rising edge polarity by writing CC2P=0 and CC2NP=0 and CC2NP=0 in the TIMx_CCER register. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.
Page 642: Figure 184. External Trigger Input Block
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 184. External trigger input block TI2F TI1F Encoder ETR0 input from AF controller mode TRGI External clock mode 1 CK_PSC ETRP Divider External clock ETRF ETR1..15 inputs from Filter /1, /2, /4, /8 mode 2 on-chip sources downcounter CK_INT...
Page 643: Capture/Compare Channels
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Figure 185. Control circuit in external clock mode 2 f CK_INT CNT_EN ETRP ETRF Counter clock = CK_CNT =CK_PSC Counter register MSv33111V3 22.3.4 Capture/Compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 644: Figure 187. Capture/Compare Channel 1 Main Circuit
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 187. Capture/Compare channel 1 main circuit APB Bus MCU-peripheral interface Input mode Output mode 16/32-bit CC1S[1] Capture/compare preload register CC1S[0] CC1S[1] CC1S[0] Compare IC1PS Capture transfer CC1E OC1PE OC1PE compare shadow register CC1G TIMx_CCMR1 (from time Comparator TIMx_EGR base unit)
Page 645: Input Capture Mode
RM0444 General-purpose timers (TIM2/TIM3/TIM4) 22.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 646: Pwm Input Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0444 22.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 647: Forced Output Mode
RM0444 General-purpose timers (TIM2/TIM3/TIM4) 22.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (ocxref/OCx) to its active level, one just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
Page 648: Pwm Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0444 The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 190.
Page 649: Figure 191. Edge-Aligned Pwm Waveforms (Arr=8)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: • When the result of the comparison or • When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen”...
Page 650 General-purpose timers (TIM2/TIM3/TIM4) RM0444 Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting mode on page 632. In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held at 100%.
Page 651: Figure 192. Center-Aligned Pwm Waveforms (Arr=8)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Figure 192. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx=7 CMS=10 or 11 CCxIF ‘1’ OCxREF CCRx=8 CMS=01 CCxIF CMS=10 CMS=11 ‘1’ OCxREF CCRx>8 CMS=01 CCxIF CMS=10 CMS=11 ‘0’...
Page 652: Asymmetric Pwm Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0444 22.3.10 Asymmetric PWM mode Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx registers.
Page 653: Clearing The Ocxref Signal On An External Event
RM0444 General-purpose timers (TIM2/TIM3/TIM4) When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.
Page 654: Figure 195. Clearing Timx Ocxref
General-purpose timers (TIM2/TIM3/TIM4) RM0444 The OCxREF signal for a given channel can be reset by applying a high level on the ETRF input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF remains low until the next update event (UEV) occurs. This function can be used only in the output compare and PWM modes.
Page 655: One-Pulse Mode
RM0444 General-purpose timers (TIM2/TIM3/TIM4) 22.3.13 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 656: 22.3.14 Retriggerable One Pulse Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0444 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 657: Encoder Interface Mode
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Figure 197. Retriggerable one-pulse mode. TRGI Counter Output MS33106V1 22.3.15 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.
Page 658: Table 118. Counting Direction Versus Encoder Signals
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Table 118. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 659: Uif Bit Remapping
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Figure 199. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward Counter down down MS33108V1 The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. Dynamic information can be obtained (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode.
Page 660: Timers And External Trigger Synchronization
General-purpose timers (TIM2/TIM3/TIM4) RM0444 22.3.18 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 661: Figure 201. Control Circuit In Gated Mode
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register.
Page 662: Figure 202. Control Circuit In Trigger Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0444 CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=00110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 663: Timer Synchronization
RM0444 General-purpose timers (TIM2/TIM3/TIM4) A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.
Page 664: Figure 205. Master/Slave Connection Example With 1 Channel Only Timers
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 205. Master/slave connection example with 1 channel only timers TIM_mstr TIM_slv Clock Prescaler Counter Output Slave tim_oc1 tim_itr CK_PSC mode control control Compare 1 Prescaler Counter Input TIM_CH1 trigger selection MSv65225V1 Note: The timers with one channel only (see Figure 205) do not feature a master mode.
Page 665: Figure 206. Gating Tim2 With Oc1Ref Of Tim3
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Configure TIM3 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM3_CR2 register). Configure the TIM3 OC1REF waveform (TIM3_CCMR1 register). Configure TIM2 to get the input trigger from TIM3 (TS=00010 in the TIM2_SMCR register).
Page 666: Figure 207. Gating Tim2 With Enable Of Tim3
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 207. Gating TIM2 with Enable of TIM3 CK_INT TIM3-CEN=CNT_EN TIM3-CNT_INIT TIM3-CNT TIM2-CNT TIM2-CNT_INIT TIM2-write CNT TIM2-TIF Write TIF = 0 MS33120V1 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 3. Refer to Figure 204 for connections.
Page 667: Figure 209. Triggering Tim2 With Enable Of Tim3
RM0444 General-purpose timers (TIM2/TIM3/TIM4) As in the previous example, both counters can be initialized before starting counting. Figure 209 shows the behavior with the same configuration as in Figure 208 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 209.
Page 668: Dma Burst Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Figure 210. Triggering TIM3 and TIM2 with TIM3 TI1 input CK_INT TIM3-TI1 TIM3-CEN=CNT_EN TIM3-CK_PSC 02 03 04 05 06 07 08 09 TIM3-CNT TIM3-TIF TIM2-CEN=CNT_EN TIM2-CK_PSC 01 02 03 04 05 06 07 08 09 TIM2-CNT TIM2-TIF MS33123V1 Note:...
Page 669: Debug Mode
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. –...
Page 670: Tim2/Tim3/Tim4 Registers
General-purpose timers (TIM2/TIM3/TIM4) RM0444 22.4 TIM2/TIM3/TIM4 registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 22.4.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 4) Address offset: 0x00 Reset value: 0x0000 UIFRE...
Page 671: Timx Control Register 2 (Timx_Cr2)(X = 2 To 4)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 672 General-purpose timers (TIM2/TIM3/TIM4) RM0444 Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Section 21.3.25: Interfacing with Hall sensors on page 575 See also Bits 6:4 MMS[2:0]: Master mode selection...
Page 673: Timx Slave Mode Control Register (Timx_Smcr)(X = 2 To 4)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) 22.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 4) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS[4:3] Res. Res. Res. SMS[3] ETPS[1:0] ETF[3:0] TS[2:0] OCCS SMS[2:0] Bits 31:22 Reserved, must be kept at reset value.
Page 674 General-purpose timers (TIM2/TIM3/TIM4) RM0444 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 675 RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bits 21, 20, 6, 5, 4 TS[4:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00000: Internal Trigger 0 (ITR0) 00001: Internal Trigger 1 (ITR1) 00010: Internal Trigger 2 (ITR2) 00011: Internal Trigger 3 (ITR3) 00100: TI1 Edge Detector (TI1F_ED) 00101: Filtered Timer Input 1 (TI1FP1)
Page 676: Timx Dma/Interrupt Enable Register (Timx_Dier)(X = 2 To 4)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 677: Timx Status Register (Timx_Sr)(X = 2 To 4)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled. Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled.
Page 678 General-purpose timers (TIM2/TIM3/TIM4) RM0444 Bits 15:13 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input...
Page 679: Timx Event Generation Register (Timx_Egr)(X = 2 To 4)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bit 2 CC2IF: Capture/Compare 2 interrupt flag Refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). 0: No compare match / No input capture occurred 1: A compare match or an input capture occurred If channel CC1 is configured as output: this flag is set when the content of the counter...
Page 680: Timx Capture/Compare Mode Register 1 [Alternate] (Timx_Ccmr1)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Bit 2 CC2G: Capture/compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 681 RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bits 9:8 CC2S[1:0]: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1.
Page 682: Timx Capture/Compare Mode Register 1 [Alternate] (Timx_Ccmr1)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 22.4.8 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 4) Address offset: 0x18 Reset value: 0x0000 0000 The same register can be used for output compare mode (this section) or for input capture mode (previous section).
Page 683 RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bits 16, 6:4 OC1M[3:0]: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 684: Timx Capture/Compare Mode Register 2 [Alternate] (Timx_Ccmr2)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 685: Timx Capture/Compare Mode Register 2 [Alternate] (Timx_Ccmr2)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
Page 686: (Timx_Ccer)(X = 2 To 4)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
Page 687: Timx Counter [Alternate] (Timx_Cnt)(X = 2 To 4)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bit 7 CC2NP: Capture/Compare 2 output Polarity. Refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity.
Page 688: Timx Counter [Alternate] (Timx_Cnt)(X = 2 To 4)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Address offset: 0x24 Reset value: 0x0000 0000 CNT[31:16] CNT[15:0] Bits 31:16 CNT[31:16]: Most significant part counter value (TIM2) Bits 15:0 CNT[15:0]: Least significant part of counter value 22.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 4) Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in TIMx_CR1 register: •...
Page 689: Timx Auto-Reload Register (Timx_Arr)(X = 2 To 4)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
Page 690: Timx Capture/Compare Register 2 (Timx_Ccr2)(X = 2 To 4)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (TIM2) Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 691: Timx Capture/Compare Register 4 (Timx_Ccr4)(X = 2 To 4)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) CCR3[31:16] CCR3[15:0] Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (TIM2) Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE).
Page 692: Timx Dma Control Register (Timx_Dcr)(X = 2 To 4)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 22.4.20 TIMx DMA control register (TIMx_DCR)(x = 2 to 4) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 693: Tim3 Option Register 1 (Tim3_Or1)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OCREF_CLR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. [1:0] Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 OCREF_CLR[1:0]: Ocref_clr source selection This bit selects the ocref_clr input source.
Page 694: Tim4 Option Register 1 (Tim4_Or1)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 22.4.24 TIM4 option register 1 (TIM4_OR1) Address offset: 0x50 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OCREF_CLR Res. Res. Res. Res. Res. Res. Res.
Page 695: Tim3 Alternate Function Option Register 1 (Tim3_Af1)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) 22.4.26 TIM3 alternate function option register 1 (TIM3_AF1) Address offset: 0x60 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2] ETRSEL[1:0] Res. Res. Res. Res. Res. Res.
Page 696: Tim2 Timer Input Selection Register (Tim2_Tisel)
General-purpose timers (TIM2/TIM3/TIM4) RM0444 22.4.28 TIM2 timer input selection register (TIM2_TISEL) Address offset: 0x68 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI3SEL[3:0] Res. Res. Res. Res. TI2SEL[3:0] Res. Res. Res. Res. TI1SEL[3:0] Bits 31:20 Reserved, must be kept at reset value.
Page 697: Tim4 Timer Input Selection Register (Tim4_Tisel)
RM0444 General-purpose timers (TIM2/TIM3/TIM4) Bits 31:20 Reserved, must be kept at reset value. Bits 19:16 TI3SEL[3:0]: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. 0000: TIM3_CH3 input 0001: COMP3 output Others: Reserved Note: Available on STM32G0B1xx and STM32G0C1xx salestypes only, otherwise reserved. Bits 15:12 Reserved, must be kept at reset value.
Page 698 General-purpose timers (TIM2/TIM3/TIM4) RM0444 Bits 11:8 TI2SEL[3:0]: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. 0000: TIM4_CH2 input 0001: COMP2 output Others: Reserved Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 TI1SEL[3:0]: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source.
Page 699: Timx Register Map
RM0444 General-purpose timers (TIM2/TIM3/TIM4) 22.4.31 TIMx register map TIMx registers are mapped as described in the table below: Table 121. TIM2/TIM3/TIM4 register map and reset values Register Offset name TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS TIMx_SMCR ETF[3:0]...
Page 700 General-purpose timers (TIM2/TIM3/TIM4) RM0444 Table 121. TIM2/TIM3/TIM4 register map and reset values (continued) Register Offset name CNT[30:16] TIMx_CNT CNT[15:0] (TIM2 only, reserved on the other timers) 0x24 Reset value TIMx_PSC PSC[15:0] 0x28 Reset value ARR[31:16] TIMx_ARR ARR[15:0] (TIM2 only, reserved on the other timers) 0x2C Reset value 0x30...
Page 701 RM0444 General-purpose timers (TIM2/TIM3/TIM4) Table 121. TIM2/TIM3/TIM4 register map and reset values (continued) Register Offset name TIM3_OR1 0x50 Reset value TIM4_OR1 0x50 Reset value ETRSEL TIM2_AF1 [3:0] 0x60 Reset value ETRSEL TIM3_AF1 [3:0] 0x60 Reset value ETRSEL TIM4_AF1 [3:0] 0x60 Reset value TIM2_TISEL TI3SEL[3:0]...
Page 702: Basic Timers (Tim6/Tim7)
Basic timers (TIM6/TIM7) RM0444 Basic timers (TIM6/TIM7) 23.1 TIM6/TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time base generation but they are also specifically used to drive the digital-to-analog converter (DAC).
Page 703: Tim6/Tim7 Functional Description
RM0444 Basic timers (TIM6/TIM7) 23.3 TIM6/TIM7 functional description 23.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 704: Figure 212. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6/TIM7) RM0444 Figure 212. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 213.
Page 705: Counting Mode
RM0444 Basic timers (TIM6/TIM7) 23.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 706: Figure 215. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6/TIM7) RM0444 Figure 215. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0035 0036 0000 0001 0002 0003 0034 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 216. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 707: Figure 217. Counter Timing Diagram, Internal Clock Divided By N
RM0444 Basic timers (TIM6/TIM7) Figure 217. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 218. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 708: Uif Bit Remapping
Basic timers (TIM6/TIM7) RM0444 Figure 219. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 709: Debug Mode
RM0444 Basic timers (TIM6/TIM7) Figure 220. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 23.3.5 Debug mode ® When the microcontroller enters the debug mode (Cortex -M0+ core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP...
Page 710 Basic timers (TIM6/TIM7) RM0444 Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit).
Page 711: Timx Control Register 2 (Timx_Cr2)(X = 6 To 7)
RM0444 Basic timers (TIM6/TIM7) 23.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 712: Timx Status Register (Timx_Sr)(X = 6 To 7)
Basic timers (TIM6/TIM7) RM0444 23.4.4 TIMx status register (TIMx_SR)(x = 6 to 7) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event.
Page 713: Timx Prescaler (Timx_Psc)(X = 6 To 7)
RM0444 Basic timers (TIM6/TIM7) Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 23.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7)
Page 714: Timx Register Map
Basic timers (TIM6/TIM7) RM0444 23.4.9 TIMx register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 122. TIMx register map and reset values Register Offset name TIMx_CR1 0x00 Reset value TIMx_CR2 [2:0] 0x04 Reset value 0x08 Reserved...
Page 715: General-Purpose Timers (Tim14)
RM0444 General-purpose timers (TIM14) General-purpose timers (TIM14) 24.1 TIM14 introduction The TIM14 general-purpose timer consists of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).
Page 716: Figure 221. General-Purpose Timer Block Diagram (Tim14)
General-purpose timers (TIM14) RM0444 Figure 221. General-purpose timer block diagram (TIM14) Internal clock (CK_INT) Trigger Enable Controller counter To other timers for cross- trigerring Auto-reload register Stop, clear CK_PSC CK_CNT CNT counter prescaler CC1I TI1[0] Input TIMx_CH1 TI1FP1 Capture/compare 1 filter &...
Page 717: Tim14 Functional Description
RM0444 General-purpose timers (TIM14) 24.3 TIM14 functional description 24.3.1 Time-base unit The main block of the timer is a 16-bit up-counter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 718: Figure 222. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM14) RM0444 Figure 222. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 223.
Page 719: Counter Modes
RM0444 General-purpose timers (TIM14) 24.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register.
Page 720: Figure 225. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM14) RM0444 Figure 225. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0036 0000 0001 0002 0003 0034 0035 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 226. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 721: Figure 227. Counter Timing Diagram, Internal Clock Divided By N
RM0444 General-purpose timers (TIM14) Figure 227. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 228. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 722: Clock Selection
General-purpose timers (TIM14) RM0444 Figure 229. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 723: Capture/Compare Channels
RM0444 General-purpose timers (TIM14) Figure 230. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT r clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 24.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 724: Input Capture Mode
General-purpose timers (TIM14) RM0444 Figure 232. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface Input mode Output mode 16/32-bit CC1S[1] Capture/compare preload register CC1S[0] CC1S[1] CC1S[0] Compare IC1PS Capture transfer CC1E OC1PE OC1PE compare shadow register CC1G TIMx_CCMR1 (from time Comparator TIMx_EGR base unit)
Page 725: Forced Output Mode
RM0444 General-purpose timers (TIM14) cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when it is written with 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 726: Output Compare Mode
General-purpose timers (TIM14) RM0444 The OCxREF signal can be forced low by writing the OCxM bits to ‘0100’ in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in the output compare mode section below.
Page 727: Pwm Mode
RM0444 General-purpose timers (TIM14) Figure 234. Output compare mode, toggle on OC1. Write B201h in the CC1R register B200 B201 TIM1_CNT 0039 003A 003B B201 003A TIM1_CCR1 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V1 24.3.8 PWM mode Pulse Width Modulation mode allows to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 728: One-Pulse Mode
General-purpose timers (TIM14) RM0444 Figure 235. Edge-aligned PWM waveforms (ARR=8) Counter register OCXREF CCRx=4 CCxIF OCXREF CCRx=8 CCxIF ‘1’ OCXREF CCRx>8 CCxIF ‘0’ OCXREF CCRx=0 CCxIF MS31093V1 24.3.9 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 729: Using Timer Output As Trigger For Other Timers (Tim14)
RM0444 General-purpose timers (TIM14) 24.3.11 Using timer output as trigger for other timers (TIM14) The timers with one channel only do not feature a master mode. However, the OC1 output signal can be used to trigger some other timers (including timers described in other sections of this document).
Page 730: Tim14 Registers
General-purpose timers (TIM14) RM0444 24.4 TIM14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 24.4.1 TIM14 control register 1 (TIM14_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE...
Page 731: Tim14 Interrupt Enable Register (Tim14_Dier)
RM0444 General-purpose timers (TIM14) Bit 2 URS: Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. 0: Any of the following events generate an UEV if enabled: – Counter overflow – Setting the UG bit 1: Only counter overflow generates an UEV if enabled.
Page 732: Tim14 Event Generation Register (Tim14_Egr)
General-purpose timers (TIM14) RM0444 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected.
Page 733: Tim14 Capture/Compare Mode Register 1 [Alternate] (Tim14_Ccmr1)
RM0444 General-purpose timers (TIM14) Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled.
Page 734 General-purpose timers (TIM14) RM0444 Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 735 RM0444 General-purpose timers (TIM14) corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. Output compare mode: OC1M Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 736: Tim14 Capture/Compare Enable Register (Tim14_Ccer)
General-purpose timers (TIM14) RM0444 Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 737: Tim14 Counter (Tim14_Cnt)
RM0444 General-purpose timers (TIM14) Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. 0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) 1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
Page 738: Tim14 Prescaler (Tim14_Psc)
General-purpose timers (TIM14) RM0444 24.4.9 TIM14 prescaler (TIM14_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
Page 739: Tim14 Timer Input Selection Register (Tim14_Tisel)
RM0444 General-purpose timers (TIM14) Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 740 General-purpose timers (TIM14) RM0444 Table 124. TIM14 register map and reset values (continued) Register Offset name TIMx_SR 0x10 Reset value TIMx_EGR 0x14 Reset value TIMx_CCMR1 OC1M CC1S Output compare [2:0] [1:0] mode Reset value 0x18 TIMx_CCMR1 CC1S IC1F[3:0] Input capture [1:0] [1:0] mode...
Page 741: General-Purpose Timers (Tim15/Tim16/Tim17)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) General-purpose timers (TIM15/TIM16/TIM17) 25.1 TIM15/TIM16/TIM17 introduction The TIM15/TIM16/TIM17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 742: Tim16/Tim17 Main Features
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.3 TIM16/TIM17 main features The TIM16/TIM17 timers include the following features: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 •...
Page 743: Figure 236. Tim15 Block Diagram
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Figure 236. TIM15 block diagram Internal clock (CK_INT) from RCC Trigger controller TRGO to other timers ITR0 Slave ITR1 Reset, enable, count controller ITR2 TRGI mode ITR3 TI1F_ED TI1FP1 TI2FP2 REP register Auto-reload register Repetition Stop, clear or up/down counter CK_PSC CK_CNT...
Page 744: Figure 237. Tim16/Tim17 Block Diagram
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 237. TIM16/TIM17 block diagram Internal clock (CK_INT) Counter Enable (CEN) REP register To other timers for Auto-reload register cross- Repetition trigerring Stop, clear or up/down counter CK_PSC CK_CNT CNT counter prescaler DTG registers CC1I TI1[0] TIMx_CH1 Input TIMx_CH1...
Page 745: Tim15/Tim16/Tim17 Functional Description
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.4 TIM15/TIM16/TIM17 functional description 25.4.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 746: Figure 238. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 238. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 239.
Page 747: Counter Modes
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.4.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR).
Page 748: Figure 240. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 240. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 34 35 36 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31078V2 Figure 241. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 749: Figure 242. Counter Timing Diagram, Internal Clock Divided By 4
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Figure 242. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31080V2 Figure 243. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 750 General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 244. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT 05 06 07 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V2 Figure 245.
Page 751: Repetition Counter
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.4.3 Repetition counter Section 25.4.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows, where N is the...
Page 752: Clock Selection
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 246. Update rate examples depending on mode and TIMx_RCR register settings Edge-aligned mode Upcounting Counter TIMx_CNT TIMx_RCR = 0 TIMx_RCR = 1 TIMx_RCR = 2 TIMx_RCR = 3 TIMx_RCR = 3 re-synchronization UEV (by SW) Update Event: preload registers transferred to active registers and update interrupt generated.
Page 753: Figure 247. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0444 General-purpose timers (TIM15/TIM16/TIM17) only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 247 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
Page 754: Capture/Compare Channels
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Select the proper TI2[x] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).
Page 755: Figure 250. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Figure 250. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1[0] TI1F_Rising TI1FP1 Filter Edge TI1[1..15] TI1F_Falling downcounter detector IC1PS TI2FP1 Divider /1, /2, /4, /8 ICF[3:0] CC1P TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising (from channel 2)
Page 756: Input Capture Mode
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 252. Output stage of capture/compare channel (channel 1) To the master mode controller Output enable ‘0’ circuit OC1REF OC1REFC OC1_DT CC1P CNT>CCR1 Output Dead-time Output TIM1_CCER mode CNT=CCR1 selector generator controller OC1N_DT Output OC1N ‘0’ OC2REF enable circuit...
Page 757: Pwm Input Mode (Only For Tim15)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when it is written with 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 758: Forced Output Mode
General-purpose timers (TIM15/TIM16/TIM17) RM0444 For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): Select the proper TI1[x] source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register.
Page 759: Output Compare Mode
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 25.4.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 760: Pwm Mode
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 255. Output compare mode, toggle on OC1 Write B201h in the CC1R register B200 B201 TIM1_CNT 0039 003A 003B B201 003A TIM1_CCR1 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V1 25.4.10 PWM mode Pulse Width Modulation mode allows a signal to be generated with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 761: Combined Pwm Mode (Tim15 Only)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 256 shows some edge- aligned PWM waveforms in an example where TIMx_ARR=8. Figure 256. Edge-aligned PWM waveforms (ARR=8) Counter register OCXREF CCRx=4 CCxIF OCXREF CCRx=8...
Page 762: Complementary Outputs And Dead-Time Insertion
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 257. Combined PWM mode on channel 1 and 2 OC2’ OC1’ OC1REF OC2REF OC1REF’ OC2REF’ OC1REFC OC1REFC’ OC1REFC = OC1REF AND OC2REF OC1REFC’ = OC1REF’ OR OC2REF’ MS31094V1 25.4.12 Complementary outputs and dead-time insertion The TIM15/TIM16/TIM17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs.
Page 763: Figure 258. Complementary Output With Dead-Time Insertion
RM0444 General-purpose timers (TIM15/TIM16/TIM17) reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: • The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. •...
Page 764: Using The Break Function
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 260. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay MS31097V1 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 25.6.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) on page 820 for delay calculation.
Page 765 RM0444 General-purpose timers (TIM15/TIM16/TIM17) The output enable signal and output levels during break are depending on several control bits: • the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event. •...
Page 766: Figure 261. Break Circuitry Overview
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 261. Break circuitry overview Lockup LOCK Core Lockup PVD LOCK System break requests SBIF flag Parity LOCK RAM parity Error ECC LOCK ECC Error BKINP BKIN inputs BKINE Software break from AF requests: BG controller BIF flag BKCMP1P BKCMP1E...
Page 767 RM0444 General-purpose timers (TIM15/TIM16/TIM17) active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs (taken over by the AFIO controller which forces a Hi-Z state) else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
Page 768: Figure 262. Output Behavior In Response To A Break
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 262. Output behavior in response to a break BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 769: Bidirectional Break Inputs
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.4.14 Bidirectional break inputs The TIM15/TIM16/TIM17 are featuring bidirectional break I/Os, as represented on Figure 263. They allow the following: • A board-level global break signal available for signaling faults to external MCUs or gate drivers, with a unique pin being both an input and an output status pin •...
Page 770: Figure 263. Output Redirection
General-purpose timers (TIM15/TIM16/TIM17) RM0444 The following procedure must be followed to re-arm the protection after a break event: • The BKDSRM bit must be set to release the output control • The software must wait until the system break condition disappears (if any) and clear the SBIF status flag (or clear it systematically before re-arming) •...
Page 771: One-Pulse Mode
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.4.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 772: Figure 264. Example Of One Pulse Mode
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Figure 264. Example of one pulse mode OC1REF TIM1_ARR TIM1_CCR1 DELAY PULSE MS31099V1 For example one may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin.
Page 773: Retriggerable One Pulse Mode (Tim15 Only)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay t min we can get.
Page 774 General-purpose timers (TIM15/TIM16/TIM17) RM0444 the counter value and a potential roll-over condition signaled by the UIFCPY flag, to be atomically read. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt).
Page 775: Timer Input Xor Function (Tim15 Only)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.4.18 Timer input XOR function (TIM15 only) The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 776: External Trigger Synchronization (Tim15 Only)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.4.19 External trigger synchronization (TIM15 only) The TIM timers are linked together internally for timer synchronization or chaining. The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Page 777: Figure 268. Control Circuit In Gated Mode
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 778: Slave Mode - Combined Reset + Trigger Mode
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we do not need any filter, so we keep IC2F=0000).
Page 779 RM0444 General-purpose timers (TIM15/TIM16/TIM17) The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes). The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address).
Page 780: Timer Synchronization (Tim15)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.4.22 Timer synchronization (TIM15) The TIMx timers are linked together internally for timer synchronization or chaining. Refer to Section 22.3.19: Timer synchronization for details. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
Page 781: Tim15 Registers
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.5 TIM15 registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 25.5.1 TIM15 control register 1 (TIM15_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE Res.
Page 782: Tim15 Control Register 2 (Tim15_Cr2)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt if enabled. These events can be: –...
Page 783 RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[2:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 784: Tim15 Slave Mode Control Register (Tim15_Smcr)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.5.3 TIM15 slave mode control register (TIM15_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS[4:3] Res. Res. Res. SMS[3] Res. Res. Res. Res. Res. Res. Res. Res.
Page 785: Tim15 Dma/Interrupt Enable Register (Tim15_Dier)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 786: Tim15 Status Register (Tim15_Sr)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bits 12:11 Reserved, must be kept at reset value. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled...
Page 787 RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/Compare 2 overcapture flag Refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode.
Page 788: Tim15 Event Generation Register (Tim15_Egr)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). 0: No compare match / No input capture occurred 1: A compare match or an input capture occurred If channel CC1 is configured as output: this flag is set when the content of the counter...
Page 789: Tim15 Capture/Compare Mode Register 1 [Alternate]
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output.
Page 790: (Tim15_Ccmr1)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC.
Page 791 RM0444 General-purpose timers (TIM15/TIM16/TIM17) corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. Output compare mode: OC2M OC1M Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 792 General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 793: Tim15 Capture/Compare Enable Register (Tim15_Ccer)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 794 General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high 1: OC1N active low CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description.
Page 795: Table 127. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Table 127. Output control bits for complementary OCx and OCxN channels with break feature (TIM15) Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not driven by the timer: Hi-Z) OCx=0 OCxN=0, OCxN_EN=0 Output Disabled (not driven...
Page 796: Tim15 Counter (Tim15_Cnt)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.5.10 TIM15 counter (TIM15_CNT) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register. Bits 30:16 Reserved, must be kept at reset value.
Page 797: Tim15 Repetition Counter Register (Tim15_Rcr)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.5.13 TIM15 repetition counter register (TIM15_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 798: Tim15 Capture/Compare Register 2 (Tim15_Ccr2)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.5.15 TIM15 capture/compare register 2 (TIM15_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 799 RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bit 27 Reserved, must be kept at reset value. Bit 26 BKDSRM: Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open- drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared.
Page 800 General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 801: Tim15 Dma Control Register (Tim15_Dcr)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5] = 0xx => DT = DTG[7:0] x t with t DTG[7:5] = 10x => DT = (64+DTG[5:0]) x t with t = 2 x t DTG[7:5] = 110 =>...
Page 802: Tim15 Alternate Register 1 (Tim15_Af1)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 803: Tim15 Input Selection Register (Tim15_Tisel)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bits 8:4 Reserved, must be kept at reset value. Bit 3 BKCMP3E: BRK COMP3 enable This bit enables the COMP3 for the timer’s BRK input. COMP3 output is ‘ORed’ with the other BRK sources. 0: COMP3 input disabled 1: COMP3 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 804: Tim15 Register Map
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIM15_CH1 input 0001: TIM2_IC1 0010: TIM3_IC1 Others: Reserved 25.5.21 TIM15 register map TIM15 registers are mapped as 16-bit addressable registers as described in the table below: Table 128. TIM15 register map and reset values Register Offset name...
Page 805 RM0444 General-purpose timers (TIM15/TIM16/TIM17) Table 128. TIM15 register map and reset values (continued) Register Offset name TIM15_CCER 0x20 Reset value TIM15_CNT CNT[15:0] 0x24 Reset value TIM15_PSC PSC[15:0] 0x28 Reset value TIM15_ARR ARR[15:0] 0x2C Reset value TIM15_RCR REP[7:0] 0x30 Reset value TIM15_CCR1 CCR1[15:0] 0x34...
Page 806 General-purpose timers (TIM15/TIM16/TIM17) RM0444 Refer to Section 2.2 on page 58 for the register boundary addresses. 806/1390 RM0444 Rev 5...
Page 807: Tim16/Tim17 Registers
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.6 TIM16/TIM17 registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 25.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) Address offset: 0x00 Reset value: 0x0000 UIFRE...
Page 808: Timx Control Register 2 (Timx_Cr2)(X = 16 To 17)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow –...
Page 809: Timx Dma/Interrupt Enable Register (Timx_Dier)(X = 16 To 17)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output.
Page 810: Timx Status Register (Timx_Sr)(X = 16 To 17)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.6.4 TIMx status register (TIMx_SR)(x = 16 to 17) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. CC1OF Res. Res. COMIF Res. Res. Res. CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode.
Page 811: Timx Event Generation Register (Timx_Egr)(X = 16 To 17)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 812: Timx Capture/Compare Mode Register 1 [Alternate] (Timx_Ccmr1)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.6.6 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17) Address offset: 0x18 Reset value: 0x0000 0000 The same register can be used for input capture mode (this section) or for output compare mode (next section).
Page 813 RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 814 General-purpose timers (TIM15/TIM16/TIM17) RM0444 OC1M Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OC1M[2:0] OC1PE OC1FE CC1S[1:0] Bits 31:17 Reserved, must be kept at reset value. Bits 15:7 Reserved, must be kept at reset value.
Page 815: Timx Capture/Compare Enable Register (Timx_Ccer)(X = 16 To 17)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bit 2 OC1FE: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
Page 816 General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Page 817: Timx Counter (Timx_Cnt)(X = 16 To 17)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Table 129. Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not driven by the timer: Hi-Z) OCx=0 OCxN=0, OCxN_EN=0 Output Disabled (not driven...
Page 818: Timx Prescaler (Timx_Psc)(X = 16 To 17)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 25.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17)
Page 819: Timx Repetition Counter Register (Timx_Rcr)(X = 16 To 17)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 820: Timx Break And Dead-Time Register (Timx_Bdtr)(X = 16 To 17)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) Address offset: 0x44 Reset value: 0x0000 0000 Res. Res. Res. BKBID Res. Res. Res. Res. Res. Res. Res. BKF[3:0] DSRM OSSR OSSI LOCK[1:0] DTG[7:0] Note: As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Page 821 RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bits 25:20 Reserved, must be kept at reset value. Bits 19:16 BKF[3:0]: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, BRK acts asynchronously 0001: f...
Page 822 General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.
Page 823: Timx Dma Control Register (Timx_Dcr)(X = 16 To 17)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e.
Page 824: Tim16 Alternate Function Register 1 (Tim16_Af1)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 25.6.17 TIM16 alternate function register 1 (TIM16_AF1) Address offset: 0x60 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BKCM BKCM BKCM BKCM BKCM BKCM Res.
Page 825: Tim16 Input Selection Register (Tim16_Tisel)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bit 3 BKCMP3E: BRK COMP3 enable This bit enables the COMP3 for the timer’s BRK input. COMP3 output is ‘ORed’ with the other BRK sources. 0: COMP3 input disabled 1: COMP3 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 826: Tim17 Alternate Function Register 1 (Tim17_Af1)
General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIM16_CH1 input 0001: LSI 0010: LSE 0011: RTC wakeup 0100: MCO2 Others: Reserved Available on STM32G0B1xx and STM32G0C1xx salestypes only, reserved otherwise. 25.6.19 TIM17 alternate function register 1 (TIM17_AF1) Address offset: 0x60 Reset value: 0x0000 0001 Res.
Page 827: Tim17 Input Selection Register (Tim17_Tisel)
RM0444 General-purpose timers (TIM15/TIM16/TIM17) Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 828 General-purpose timers (TIM15/TIM16/TIM17) RM0444 Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input 0000: TIM17_CH1 input 0001: HSI48/256 0010: HSE/32 0011: MCO 0100: MCO2 Others: Reserved 1. Available on STM32G0B1xx and STM32G0C1xx salestypes only, reserved otherwise. 828/1390 RM0444 Rev 5...
Page 829: Tim16/Tim17 Register Map
RM0444 General-purpose timers (TIM15/TIM16/TIM17) 25.6.21 TIM16/TIM17 register map TIM16/TIM17 registers are mapped as 16-bit addressable registers as described in the table below: Table 130. TIM16/TIM17 register map and reset values Register Offset name TIMx_CR1 [1:0] 0x00 Reset value TIMx_CR2 0x04 Reset value TIMx_DIER 0x0C...
Page 830 General-purpose timers (TIM15/TIM16/TIM17) RM0444 Table 130. TIM16/TIM17 register map and reset values (continued) Register Offset name TIMx_RCR REP[7:0] 0x30 Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_BDTR BKF[3:0] DTG[7:0] 0x44 [1:0] Reset value TIMx_DCR DBL[4:0] DBA[4:0] 0x48 Reset value TIMx_DMAR DMAB[15:0] 0x4C Reset value...
Page 831: Low-Power Timer (Lptim)
RM0444 Low-power timer (LPTIM) Low-power timer (LPTIM) 26.1 Introduction The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a “Pulse Counter”...
Page 832: Lptim Implementation
Low-power timer (LPTIM) RM0444 26.3 LPTIM implementation Table 131 describes LPTIM implementation on STM32G0x1 devices: the full set of features is implemented in LPTIM1. LPTIM2 supports a smaller set of features, but is otherwise identical to LPTIM1. Table 131. STM32G0x1 LPTIM features LPTIM modes/features LPTIM1 LPTIM2...
Page 833: Lptim Pins And Internal Signals
RM0444 Low-power timer (LPTIM) 26.4.2 LPTIM pins and internal signals The following tables provide the list of LPTIM pins and internal signals, respectively. Table 132. LPTIM input/output pins Names Signal type Description LPTIM_IN1 Digital input LPTIM Input 1 from GPIO pin on mux input 0 LPTIM_IN2 Digital input LPTIM Input 2 from GPIO pin on mux input 0...
Page 834: Table 135. Lptim2 External Trigger Connection
Low-power timer (LPTIM) RM0444 Table 134. LPTIM1 external trigger connection (continued) TRIGSEL External trigger lptim_ext_trig6 COMP1_OUT lptim_ext_trig7 COMP2_OUT Table 135. LPTIM2 external trigger connection TRIGSEL External trigger lptim_ext_trig0 GPIO pin as LPTIM2_ETR alternate function lptim_ext_trig1 RTC ALARM A lptim_ext_trig2 RTC ALARM B lptim_ext_trig3 TAMP1 input detection lptim_ext_trig4...
Page 835: Lptim Reset And Clocks
RM0444 Low-power timer (LPTIM) 26.4.4 LPTIM reset and clocks The LPTIM can be clocked using several clock sources. It can be clocked using an internal clock signal which can be PCLK (APB clock) or any other embedded oscillator selectable through the RCC (see RCC section for more details). Also, the LPTIM can be clocked using an external clock signal injected on its external Input1.
Page 836: Prescaler
Low-power timer (LPTIM) RM0444 Figure 271. Glitch filter timing diagram CLKMUX Input Filter out 2 consecutive samples 2 consecutive samples Filtered MS32490V1 Note: In case no internal clock signal is provided, the digital filter must be deactivated by setting the CKFLT and TRGFLT bits to ‘0’. In that case, an external analog filter may be used to protect the LPTIM external inputs against glitches.
Page 837: Operating Mode
RM0444 Low-power timer (LPTIM) The external triggers are considered asynchronous signals for the LPTIM. So after a trigger detection, a two-counter-clock period latency is needed before the timer starts running due to the synchronization. If a new trigger event occurs when the timer is already started it will be ignored (unless timeout function is enabled).
Page 838: Figure 273. Lptim Output Waveform, Single Counting Mode Configuration
Low-power timer (LPTIM) RM0444 Figure 273. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) LPTIM_ARR Compare Discarded trigger External trigger event MSv39231V2 In case of software start (TRIGEN[1:0] = ‘00’), the SNGSTRT setting will start the counter for one-shot counting.
Page 839: Timeout Function
RM0444 Low-power timer (LPTIM) 26.4.9 Timeout function The detection of an active edge on one selected trigger input can be used to reset the LPTIM counter. This feature is controlled through the TIMOUT bit. The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart.
Page 840: Register Update
Low-power timer (LPTIM) RM0444 Figure 275. Waveform generation LPTIM_ARR Compare One shot Pol = 0 Set once One shot Pol = 1 Set once MS32467V2 26.4.11 Register update The LPTIM_ARR register and LPTIM_CMP register are updated immediately after the APB bus write operation, or at the end of the current period if the timer is already started.
Page 841: Counter Mode
RM0444 Low-power timer (LPTIM) 26.4.12 Counter mode The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. The CKSEL and COUNTMODE bits control which source will be used for updating the counter. In case the LPTIM is configured to count external events on Input1, the counter can be updated following a rising edge, falling edge or both edges depending on the value written to the CKPOL[1:0] bits.
Page 842: Timer Counter Reset
Low-power timer (LPTIM) RM0444 26.4.14 Timer counter reset In order to reset the content of LPTIM_CNT register to zero, two reset mechanisms are implemented: • The synchronous reset mechanism: the synchronous reset is controlled by the COUNTRST bit in the LPTIM_CR register. After setting the COUNTRST bit-field to '1', the reset signal is propagated in the LPTIM kernel clock domain.
Page 843: Table 140. Encoder Counting Scenarios
RM0444 Low-power timer (LPTIM) To activate the Encoder mode the ENC bit has to be set to ‘1’. The LPTIM must first be configured in Continuous mode. When Encoder mode is active, the LPTIM counter is modified automatically following the speed and the direction of the incremental encoder.
Page 844: Debug Mode
Low-power timer (LPTIM) RM0444 Figure 276. Encoder mode counting sequence Counter down MS32491V1 26.4.16 Debug mode When the microcontroller enters debug mode (core halted), the LPTIM counter either continues to work normally or stops, depending on the DBG_LPTIM_STOP configuration bit in the DBG module.
Page 845: Lptim Interrupts
RM0444 Low-power timer (LPTIM) 26.6 LPTIM interrupts The following events generate an interrupt/wake-up event, if they are enabled through the LPTIM_IER register: • Compare match • Auto-reload match (whatever the direction if encoder mode) • External trigger event • Autoreload register write completed •...
Page 846: Lptim Interrupt And Status Register (Lptim_Isr)
Low-power timer (LPTIM) RM0444 26.7.1 LPTIM interrupt and status register (LPTIM_ISR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 847: Lptim Interrupt Clear Register (Lptim_Icr)
RM0444 Low-power timer (LPTIM) 26.7.2 LPTIM interrupt clear register (LPTIM_ICR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN ARRO CMPO EXTTR ARRM CMPM Res. Res.
Page 848: Lptim Configuration Register (Lptim_Cfgr)
Low-power timer (LPTIM) RM0444 Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWNIE: Direction change to down Interrupt Enable DOWN interrupt disabled DOWN interrupt enabled Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 26.3: LPTIM implementation.
Page 849 RM0444 Low-power timer (LPTIM) Bit 24 ENC: Encoder mode enable The ENC bit controls the Encoder mode 0: Encoder mode disabled 1: Encoder mode enabled Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 26.3: LPTIM implementation.
Page 850 Low-power timer (LPTIM) RM0444 Bits 15:13 TRIGSEL[2:0]: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext_trig0 001: lptim_ext_trig1 010: lptim_ext_trig2 011: lptim_ext_trig3 100: lptim_ext_trig4 101: lptim_ext_trig5 110: lptim_ext_trig6...
Page 851: Lptim Control Register (Lptim_Cr)
RM0444 Low-power timer (LPTIM) Bits 4:3 CKFLT[1:0]: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is...
Page 852: Lptim Compare Register (Lptim_Cmp)
Low-power timer (LPTIM) RM0444 Bits 31:5 Reserved, must be kept at reset value. Bit 4 RSTARE: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content. Bit 3 COUNTRST: Counter reset This bit is set by software and cleared by hardware.
Page 853: Lptim Autoreload Register (Lptim_Arr)
RM0444 Low-power timer (LPTIM) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP[15:0]: Compare value CMP is the compare value used by the LPTIM. Caution: The LPTIM_CMP register must only be modified when the LPTIM is enabled (ENABLE bit set to ‘1’).
Page 854: Lptim Configuration Register 2 (Lptim_Cfgr2)
Low-power timer (LPTIM) RM0444 26.7.9 LPTIM configuration register 2 (LPTIM_CFGR2) Address offset: 0x024 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 855: Lptim Register Map
RM0444 Low-power timer (LPTIM) 26.7.10 LPTIM register map The following table summarizes the LPTIM registers. Table 143. LPTIM register map and reset values Offset Register name LPTIM_ISR 0x000 0 0 0 0 0 0 0 Reset value LPTIM_ICR 0x004 0 0 0 0 0 0 0 Reset value LPTIM_IER 0x008...
Page 856 Low-power timer (LPTIM) RM0444 If LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 26.3: LPTIM implementation. Refer to Section 2.2 on page 58 for the register boundary addresses. 856/1390 RM0444 Rev 5...
Page 857: Infrared Interface (Irtim)
RM0444 Infrared interface (IRTIM) Infrared interface (IRTIM) An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared LED to perform remote control functions. It uses internal connections with USART1, USART4 (on STM32G071/81/B1/C1xx) or USART2 (STM32G031/41/51/61xx), TIM16 and TIM17 as shown in Figure 277.
Page 858: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) RM0444 Independent watchdog (IWDG) 28.1 Introduction The devices feature an embedded watchdog peripheral that offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral detects and solves malfunctions due to software failure, and triggers system reset when the counter reaches a given timeout value.
Page 859: Window Option
RM0444 Independent watchdog (IWDG) When the independent watchdog is started by writing the value 0x0000 CCCC in the IWDG key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the IWDG key register (IWDG_KR), the...
Page 860: Hardware Watchdog
Independent watchdog (IWDG) RM0444 28.3.3 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the IWDG key register (IWDG_KR) is written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window.
Page 861: Iwdg Registers
RM0444 Independent watchdog (IWDG) 28.4 IWDG registers Refer to Section 1.2 on page 53 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 28.4.1 IWDG key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
Page 862: Iwdg Prescaler Register (Iwdg_Pr)
Independent watchdog (IWDG) RM0444 28.4.2 IWDG prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 863: Iwdg Reload Register (Iwdg_Rlr)
RM0444 Independent watchdog (IWDG) 28.4.3 IWDG reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 864: Iwdg Status Register (Iwdg_Sr)
Independent watchdog (IWDG) RM0444 28.4.4 IWDG status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 865: Iwdg Window Register (Iwdg_Winr)
RM0444 Independent watchdog (IWDG) 28.4.5 IWDG window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WIN[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 866: Iwdg Register Map
Independent watchdog (IWDG) RM0444 28.4.6 IWDG register map The following table gives the IWDG register map and reset values. Table 144. IWDG register map and reset values Register Offset name IWDG_KR KEY[15:0] 0x00 Reset value IWDG_PR PR[2:0] 0x04 Reset value IWDG_RLR RL[11:0] 0x08...
Page 867: System Window Watchdog (Wwdg)
RM0444 System window watchdog (WWDG) System window watchdog (WWDG) 29.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the down-counter before the T6 bit becomes cleared.
Page 868: Wwdg Block Diagram
System window watchdog (WWDG) RM0444 29.3.1 WWDG block diagram Figure 279. Watchdog block diagram WWDG Register interface CMP = 1 when T[6:0] > W[6:0] W[6:0] WWDG_CFR wwdg_out_rst WWDG_SR WDGA Write to WWDG_CR T[6:0] readback WWDG_CR T[6:0] wwdg_it EWIF cnt_out preload 7-bit DownCounter (CNT) WDGTB pclk...
Page 869: Figure 280. Window Watchdog Timing Diagram
RM0444 System window watchdog (WWDG) Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 280. Window watchdog timing diagram CNT DownCounter Refresh not allowed Refresh allowed T[6:0] W[6:0] 0x3F Time WDGTB...
Page 870: Debug Mode
System window watchdog (WWDG) RM0444 As an example, lets assume APB frequency is equal to 48 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 1 48000 4096 43.69ms Refer to the datasheet for the minimum and maximum values of the t WWDG 29.3.5 Debug mode...
Page 871: Wwdg Configuration Register (Wwdg_Cfr)
RM0444 System window watchdog (WWDG) Bits 31:8 Reserved, must be kept at reset value. Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
Page 872: Wwdg Status Register (Wwdg_Sr)
System window watchdog (WWDG) RM0444 29.5.3 WWDG status register (WWDG_SR) Address offset: 0x008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 873: Real-Time Clock (Rtc)
RM0444 Real-time clock (RTC) Real-time clock (RTC) 30.1 Introduction The RTC provides an automatic wakeup to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar with programmable alarm interrupts. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset).
Page 874: Rtc Functional Description
Real-time clock (RTC) RM0444 30.3 RTC functional description 30.3.1 RTC block diagram Figure 281. RTC block diagram rtc_tamp_evt rtc_its Time stamp detection RTC_TS Time stamp registers RTC_TSTR RTC_TSDR RTC_TSSR RTC_REFIN ck_spre RTC_CALR RTC_PRER RTC_PRER (default 1 Hz) rtc_ker_ck Asynchronous Synchronous Smooth prescaler prescaler...
Page 875: Rtc Pins And Internal Signals
RM0444 Real-time clock (RTC) 30.3.2 RTC pins and internal signals Table 146. RTC input/output pins Pin name Signal type Description RTC_TS Input RTC timestamp input RTC_REFIN Input RTC 50 or 60 Hz reference clock input RTC_OUT1 Output RTC output 1 RTC_OUT2 Output RTC output 2...
Page 876: Gpios Controlled By The Rtc And Tamp
Real-time clock (RTC) RM0444 Table 148. RTC interconnection Signal name Source/destination From power controller (PWR): main power loss/switch to V detection rtc_its output rtc_tamp_evt From TAMP peripheral: tamp_evt rtc_calovf To TAMP peripheral: tamp_itamp5 The triggers outputs can be used as triggers for other peripherals. 30.3.3 GPIOs controlled by the RTC and TAMP The GPIOs included in the Battery Backup Domain (V...
Page 877 RM0444 Real-time clock (RTC) Table 149. PC13 configuration (continued) PC13 Pin function 01 or 10 or Don’t Don’t Don’t Don’t No pull care care care care 01 or 10 or TAMPALRM output 01 or Open-Drain 10 or Internal Don’t Don’t Don’t Don’t pull-up...
Page 878: Clock And Prescalers
Real-time clock (RTC) RM0444 Table 149. PC13 configuration (continued) PC13 Pin function Don’t care Wakeup pin or Standard Don’t Don’t GPIO care care Don’t Don’t care care 1. OD: open drain; PP: push-pull. 2. In this configuration the GPIO must be configured in input. In addition, it is possible to output RTC_OUT2 on PA4 pin thanks to OUT2EN bit.
Page 879: Real-Time Clock And Calendar
RM0444 Real-time clock (RTC) A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 281: RTC block diagram): • A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register.
Page 880: Programmable Alarms
Real-time clock (RTC) RM0444 BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers. When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD = 0 mode, the frequency of the APB clock (f ) must be at least 7 times the frequency of the RTC clock RTCCLK The shadow registers are reset by system reset.
Page 881: Rtc Initialization And Configuration
RM0444 Real-time clock (RTC) the RTC_SR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value). The WUTF flag must then be cleared by software. When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR register, it can exit the device from low-power modes.
Page 882 Real-time clock (RTC) RM0444 Set INIT bit to 1 in the RTC_ICSR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated. Poll INITF bit of in the RTC_ICSR register. The initialization phase mode is entered when INITF is set to 1.
Page 883: Reading The Calendar
RM0444 Real-time clock (RTC) The wakeup timer restarts down-counting.The WUTWF bit is cleared up to 2 RTCCLK clocks cycles after WUTE is cleared, due to clock synchronization. 30.3.9 Reading the calendar When BYPSHAD control bit is cleared in the RTC_CR register To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency (f ) must be equal to or greater than seven times the RTC clock...
Page 884: Resetting The Rtc
Real-time clock (RTC) RM0444 Note: While BYPSHAD = 1, instructions which read the calendar registers require one extra APB cycle to complete. 30.3.10 Resetting the RTC The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ICSR) are reset to their default values by all available system reset sources.
Page 885: Rtc Reference Clock Detection
RM0444 Real-time clock (RTC) Caution: This synchronization feature is not compatible with the reference clock detection feature: firmware must not write to RTC_SHIFTR when REFCKON = 1. 30.3.12 RTC reference clock detection The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN, which is usually the mains frequency (50 or 60 Hz).
Page 886 Real-time clock (RTC) RM0444 The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle: • Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32- second cycle.
Page 887: Timestamp Function
RM0444 Real-time clock (RTC) Verifying the RTC calibration RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision. Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.
Page 888: Calibration Clock Output
Real-time clock (RTC) RM0444 The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when an internal timestamp event is detected. The internal timestamp event is generated by the switch to the V supply. When a timestamp event occurs, due to internal or external event, the timestamp flag bit (TSF) in RTC_SR register is set.
Page 889: Rtc Low-Power Modes
RM0444 Real-time clock (RTC) When the TAMPOE control bit is set is the RTC_CR, all external and internal tamper flags are ORed and routed to the TAMPALRM output. If OSEL = 00 the TAMPALRM output reflects only the tampers flags. If OSEL ≠ 00, the signal on TAMPALRM provides both tamper flags and alarm A, B, or wakeup flag.
Page 890: Rtc Interrupts
Backup domain reset value: 0x0000 0000 System reset value: 0x0000 0000 (when BYPSHAD = 0, not affected when BYPSHAD = 1) Res. Res. Res. Res. Res. Res. Res. Res. Res. HT[1:0] HU[3:0] Res. MNT[2:0] MNU[3:0] Res. ST[2:0] SU[3:0] 890/1390 RM0444 Rev 5...
Page 891: Rtc Date Register (Rtc_Dr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format 30.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register.
Page 892: Rtc Sub Second Register (Rtc_Ssr)
Real-time clock (RTC) RM0444 Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format Note: The calendar is frozen when reaching the maximum value, and can’t roll over. 30.6.3 RTC sub second register (RTC_SSR) Address offset: 0x08...
Page 893 RM0444 Real-time clock (RTC) Bits 31:17 Reserved, must be kept at reset value. Bit 16 RECALPF: Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0.
Page 894: Rtc Prescaler Register (Rtc_Prer)
Real-time clock (RTC) RM0444 Bit 2 WUTWF: Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Wakeup timer configuration update not allowed except in initialization mode 1: Wakeup timer configuration update allowed Bit 1 ALRBWF: Alarm B write flag...
Page 895: Rtc Wakeup Timer Register (Rtc_Wutr)
RM0444 Real-time clock (RTC) 30.6.6 RTC wakeup timer register (RTC_WUTR) This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page 881.
Page 896 Real-time clock (RTC) RM0444 Bit 31 OUT2EN: RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL ≠...
Page 897 RM0444 Real-time clock (RTC) Bit 19 COSEL: Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. 0: Calibration output is 512 Hz 1: Calibration output is 1 Hz These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255).
Page 898: Rtc Write Protection Register (Rtc_Wpr)
Real-time clock (RTC) RM0444 Bit 6 FMT: Hour format 0: 24 hour/day format 1: AM/PM hour format Bit 5 BYPSHAD: Bypass the shadow registers 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters.
Page 899: Rtc Calibration Register (Rtc_Calr)
RM0444 Real-time clock (RTC) Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 KEY[7:0]: Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection.
Page 900: Rtc Shift Control Register (Rtc_Shiftr)
Real-time clock (RTC) RM0444 Bit 13 CALW16: Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section 30.3.13: RTC smooth digital calibration.
Page 901: Rtc Timestamp Time Register (Rtc_Tstr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. 30.6.12 RTC timestamp date register (RTC_TSDR) The content of this register is valid only when TSF is set to 1 in RTC_SR.
Page 902: Rtc Timestamp Sub Second Register (Rtc_Tsssr)
Real-time clock (RTC) RM0444 Bits 31:16 Reserved, must be kept at reset value. Bits 15:13 WDU[2:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format 30.6.13...
Page 903: Rtc Alarm A Register (Rtc_Alrmar)
Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. RM0444 Rev 5...
Page 904: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
Real-time clock (RTC) RM0444 30.6.15 RTC alarm A sub second register (RTC_ALRMASSR) This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 881.
Page 905: Rtc Alarm B Register (Rtc_Alrmbr)
Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format RM0444 Rev 5...
Page 906: Rtc Alarm B Sub Second Register (Rtc_Alrmbssr)
Real-time clock (RTC) RM0444 30.6.17 RTC alarm B sub second register (RTC_ALRMBSSR) This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section : RTC register write protection.
Page 907: Rtc Masked Interrupt Status Register (Rtc_Misr)
RM0444 Real-time clock (RTC) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ITSF TSOVF WUTF ALRBF ALRAF Bits 31:6 Reserved, must be kept at reset value. Bit 5 ITSF: Internal timestamp flag This flag is set by hardware when a timestamp on the internal event occurs.
Page 908: Rtc Status Clear Register (Rtc_Scr)
Real-time clock (RTC) RM0444 Bits 31:6 Reserved, must be kept at reset value. Bit 5 ITSMF: Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised. Bit 4 TSOVMF: Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set.
Page 909 RM0444 Real-time clock (RTC) Bit 2 CWUTF: Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register. Bit 1 CALRBF: Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register. Bit 0 CALRAF: Clear alarm A flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
Page 910: Rtc Register Map
Real-time clock (RTC) RM0444 30.6.21 RTC register map Table 154. RTC register map and reset values Offset Register RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0] DU[3:0] [1:0] 0x04 Reset value RTC_SSR SS[15:0]...
Page 911 RM0444 Real-time clock (RTC) Table 154. RTC register map and reset values (continued) Offset Register RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x40 Reset value RTC_ MASKSS SS[14:0] ALRMASSR [3:0] 0x44 Reset value RTC_ALRMBR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0]...
Page 912: Tamper And Backup Registers (Tamp)
Tamper and backup registers (TAMP) RM0444 Tamper and backup registers (TAMP) 31.1 Introduction 5 32-bit backup registers are retained in all low-power modes and also in V mode. They can be used to store sensitive data as their content is protected by an tamper detection circuit.
Page 913: Tamp Functional Description
RM0444 Tamper and backup registers (TAMP) 31.3 TAMP functional description 31.3.1 TAMP block diagram Figure 282. TAMP block diagram tamp_ker_ck clock domain TAMP1F Tamper detection TAMP_IN1 EDGE detection tamp_trg1 LEVEL detection TAMP2F Tamper detection TAMP_IN2 EDGE detection tamp_trg2 LEVEL detection TAMPxF Tamper detection TAMP_INx...
Page 914: Tamp Pins And Internal Signals
HSE monitoring tamp_itamp5 RTC calendar overflow (rtc_calovf) tamp_itamp6 ST manufacturer readout 31.3.3 TAMP register write protection After system reset, the TAMP registers (including backup registers) are protected against parasitic write access by the DBP bit in the power control peripheral (refer to the PWR power control section).
Page 915: Tamper Detection
RM0444 Tamper and backup registers (TAMP) 31.3.4 Tamper detection The tamper detection can be configured for the following purposes: • erase the backup registers (default configuration) • generate an interrupt, capable to wakeup from Stop and Standby mode • generate a hardware trigger for the low-power timers TAMP backup registers The backup registers (TAMP_BKPxR) are not reset by system reset or when the device wakes up from Standby mode.
Page 916 Tamper and backup registers (TAMP) RM0444 This feature is available only when the tamper is configured in the Level detection with filtering on tamper inputs (passive mode) mode (TAMPFLT ≠ 00 and active mode is not selected). Timestamp on tamper event With TAMPTS set to 1 in the RTC_CR, any tamper event causes a timestamp to occur.
Page 917: Tamp Low-Power Modes
RM0444 Tamper and backup registers (TAMP) 31.4 TAMP low-power modes Table 158. Effect of low-power modes on TAMP Mode Description No effect. Sleep TAMP interrupts cause the device to exit the Sleep mode. No effect on all features, except for level detection with filtering mode which remain active only when the clock source is LSE or LSI.
Page 918: Tamp Control Register 1 (Tamp_Cr1)
Bit 21 ITAMP6E: Internal tamper 6 enable: ST manufacturer readout 0: Internal tamper 6 disabled. 1: Internal tamper 6 enabled: a tamper is generated in case of ST manufacturer readout. Bit 20 ITAMP5E: Internal tamper 5 enable: RTC calendar overflow 0: Internal tamper 5 disabled.
Page 919: Tamp Control Register 2 (Tamp_Cr2)
RM0444 Tamper and backup registers (TAMP) Bit 2 TAMP3E: Tamper detection on TAMP_IN3 enable 0: Tamper detection on TAMP_IN3 is disabled. 1: Tamper detection on TAMP_IN3 is enabled. Bit 1 TAMP2E: Tamper detection on TAMP_IN2 enable 0: Tamper detection on TAMP_IN2 is disabled. 1: Tamper detection on TAMP_IN2 is enabled.
Page 920: Tamp Filter Control Register (Tamp_Fltcr)
Tamper and backup registers (TAMP) RM0444 Bits 22:19 Reserved, must be kept at reset value. Bit 18 TAMP3MSK: Tamper 3 mask 0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. 1: Tamper 3 event generates a trigger event.
Page 921: Tamp Interrupt Enable Register (Tamp_Ier)
RM0444 Tamper and backup registers (TAMP) Bits 31:8 Reserved, must be kept at reset value. Bit 7 TAMPPUDIS: TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample. 0: Precharge TAMP_INx pins before sampling (enable internal pull-up) 1: Disable precharge of TAMP_INx pins.
Page 922: Tamp Status Register (Tamp_Sr)
Bit 23 Reserved, must be kept at reset value. Bit 22 Reserved, must be kept at reset value. Bit 21 ITAMP6IE: Internal tamper 6 interrupt enable: ST manufacturer readout 0: Internal tamper 6 interrupt disabled. 1: Internal tamper 6 interrupt enabled.
Page 923: Tamp Masked Interrupt Status Register (Tamp_Misr)
Bit 23 Reserved, must be kept at reset value. Bit 22 Reserved, must be kept at reset value. Bit 21 ITAMP6F: ST manufacturer readout tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6.
Page 924: Tamp Status Clear Register (Tamp_Scr)
Tamper and backup registers (TAMP) RM0444 Bit 21 ITAMP6MF: ST manufacturer readout tamper interrupt masked flag This flag is set by hardware when the internal tamper 6 interrupt is raised. Bit 20 ITAMP5MF: RTC calendar overflow tamper interrupt masked flag This flag is set by hardware when the internal tamper 5 interrupt is raised.
Page 925: Tamp Backup X Register (Tamp_Bkpxr)
RM0444 Tamper and backup registers (TAMP) Bit 17 Reserved, must be kept at reset value. Bit 16 Reserved, must be kept at reset value. Bits 15:3 Reserved, must be kept at reset value. Bit 2 CTAMP3F: Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register.
Page 926: Tamp Register Map
Tamper and backup registers (TAMP) RM0444 31.6.9 TAMP register map Table 160. TAMP register map and reset values Offset Register TAMP_CR1 0x00 Reset value TAMP_CR2 0x04 Reset value TAMP_FLTCR 0x0C Reset value TAMP_IER 0x2C Reset value TAMP_SR 0x30 Reset value TAMP_MISR 0x34 Reset value...
Page 927: Inter-Integrated Circuit (I2C) Interface
RM0444 Inter-integrated circuit (I2C) interface Inter-integrated circuit (I2C) interface 32.1 Introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
Page 928: I2C Implementation
Inter-integrated circuit (I2C) interface RM0444 The following additional features are also available depending on the product implementation (see Section 32.3: I2C implementation): • SMBus specification rev 3.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control –...
Page 929: I2C1 Block Diagram
RM0444 Inter-integrated circuit (I2C) interface If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also available. 32.4.1 I2C1 block diagram The block diagram of the I2C1 interface is shown in Figure 283. Figure 283. I2C1 block diagram I2CCLK I2c_ker_ck Data control...
Page 930: I2C2 Block Diagram
Inter-integrated circuit (I2C) interface RM0444 32.4.2 I2C2 block diagram The block diagram of the I2C2 interface is shown in Figure 284. Figure 284. I2C2 block diagram I2CCLK PCLK Data control Digital Analog Shift register noise noise GPIO I2C1_SDA filter filter logic SMBUS generation/...
Page 931: I2C Pins And Internal Signals
RM0444 Inter-integrated circuit (I2C) interface 32.4.3 I2C pins and internal signals Table 162. I2C input/output pins Pin name Signal type Description I2C_SDA Bidirectional I2C data I2C_SCL Bidirectional I2C clock I2C_SMBA Bidirectional SMBus Alert Table 163. I2C internal input/output signals Internal signal name Signal type Description I2C kernel clock, also named I2CCLK in this...
Page 932: I2C Initialization
Inter-integrated circuit (I2C) interface RM0444 By default, it operates in slave mode. The interface automatically switches from slave to master when it generates a START condition, and from master to slave if an arbitration loss or a STOP generation occurs, allowing multimaster capability. Communication flow In Master mode, the I2C interface initiates a data transfer and generates the clock signal.
Page 933: Table 164. Comparison Of Analog Vs. Digital Filters
RM0444 Inter-integrated circuit (I2C) interface suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-mode Plus. The user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by configuring the DNF[3:0] bit in the I2C_CR1 register. When the digital filter is enabled, the level of the SCL or the SDA line is internally changed only if it remains stable for more than DNF x I2CCLK periods.
Page 934: Figure 286. Setup And Hold Timings
Inter-integrated circuit (I2C) interface RM0444 I2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 286.
Page 935: Table 165. I2C-Smbus Specification Data Setup And Hold Times
RM0444 Inter-integrated circuit (I2C) interface • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is where = SDADEL x t = (PRESC+1) SDADEL PRESC I2CCLK PRESC I2CCLK impacts the hold time SDADEL HD;DAT.
Page 936 Inter-integrated circuit (I2C) interface RM0444 Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x t , in both transmission I2CCLK and reception modes. In transmission mode, in case the data is not yet written in I2C_TXDR when SDADEL counter is finished, the I2C keeps on stretching SCL low until the next data is written.
Page 937: Software Reset
RM0444 Inter-integrated circuit (I2C) interface Figure 287. I2C initialization flowchart Initial settings Clear PE bit in I2C_CR1 Configure ANFOFF and DNF[3:0] in I2C_CR1 Configure PRESC[3:0], SDADEL[3:0], SCLDEL[3:0], SCLH[7:0], SCLL[7:0] in I2C_TIMINGR Configure NOSTRETCH in I2C_CR1 Set PE bit in I2C_CR1 MS19847V2 32.4.7 Software reset...
Page 938: Data Transfer
Inter-integrated circuit (I2C) interface RM0444 32.4.8 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0).
Page 939: Figure 289. Data Transmission
RM0444 Inter-integrated circuit (I2C) interface Transmission If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in I2C_TXDR, SCL line is stretched low until I2C_TXDR is written.
Page 940: I2C Slave Mode
Inter-integrated circuit (I2C) interface RM0444 When RELOAD=0 in master mode, the counter can be used in 2 modes: • Automatic end mode (AUTOEND = ‘1’ in the I2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred.
Page 941 RM0444 Inter-integrated circuit (I2C) interface By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the I2C must be configured with NOSTRETCH=1 in the I2C_CR1 register.
Page 942: Figure 290. Slave Initialization Flowchart
Inter-integrated circuit (I2C) interface RM0444 Slave Byte Control mode In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant with SMBus standards.
Page 943 RM0444 Inter-integrated circuit (I2C) interface Slave transmitter A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register. The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be transmitted.
Page 944: Figure 291. Transfer Sequence Flowchart For I2C Slave Transmitter
Inter-integrated circuit (I2C) interface RM0444 Figure 291. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 0 Slave transmission Slave initialization I2C_ISR.ADDR stretched Read ADDCODE and DIR in I2C_ISR Optional: Set I2C_ISR.TXE = 1 Set I2C_ICR.ADDRCF I2C_ISR.TXIS Write I2C_TXDR.TXDATA MS19851V2 944/1390 RM0444 Rev 5...
Page 945: Figure 292. Transfer Sequence Flowchart For I2C Slave Transmitter
RM0444 Inter-integrated circuit (I2C) interface Figure 292. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 1 Slave transmission Slave initialization I2C_ISR.STOPF I2C_ISR.TXIS Write I2C_TXDR.TXDATA Optional: Set I2C_ISR.TXE = 1 and I2C_ISR.TXIS=1 Set I2C_ICR.STOPCF MS19852V2 RM0444 Rev 5 945/1390...
Page 946: Figure 293. Transfer Bus Diagrams For I2C Slave Transmitter
Inter-integrated circuit (I2C) interface RM0444 Figure 293. Transfer bus diagrams for I2C slave transmitter legend: Example I2C slave transmitter 3 bytes with 1st data flushed, NOSTRETCH=0: transmission ADDR TXIS TXIS TXIS TXIS reception SCL stretch Address data3 data1 data2 EV4 EV5 EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF EV2: TXIS ISR: wr data1 EV3: TXIS ISR: wr data2...
Page 947: Figure 294. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0
RM0444 Inter-integrated circuit (I2C) interface Slave receiver RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is set in I2C_CR1. RXNE is cleared when I2C_RXDR is read. When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an interrupt is generated.
Page 948: Figure 295. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1
Inter-integrated circuit (I2C) interface RM0444 Figure 295. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 Slave reception Slave initialization I2C_ISR.STOPF I2C_ISR.RXNE Set I2C_ICR.STOPCF Read I2C_RXDR.RXDATA MS19856V2 Figure 296. Transfer bus diagrams for I2C slave receiver legend: Example I2C slave receiver 3 bytes, NOSTRETCH=0: transmission ADDR RXNE...
Page 949: I2C Master Mode
RM0444 Inter-integrated circuit (I2C) interface 32.4.10 I2C master mode I2C master initialization Before enabling the peripheral, the I2C master clock must be configured by setting the SCLH and SCLL bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
Page 950: Figure 297. Master Clock Generation
Inter-integrated circuit (I2C) interface RM0444 Figure 297. Master clock generation SCL master clock generation SCL high level detected SCLH counter starts SCLH SYNC2 SCLL SYNC1 SCL low level detected SCL released SCLL counter starts SCL driven low SCL master clock synchronization SCL high level detected SCL high level detected SCL high level detected...
Page 951: Table 167. I2C-Smbus Specification Clock Timings
RM0444 Inter-integrated circuit (I2C) interface Table 167. I C-SMBus specification clock timings Standard- Fast-mode Fast-mode SMBus mode (Sm) (Fm) Plus (Fm+) Symbol Parameter Unit SCL clock frequency 1000 Hold time (repeated) START condition 0.26 µs HD:STA Set-up time for a repeated START 0.26 µs SU:STA...
Page 952: Figure 298. Master Initialization Flowchart
Inter-integrated circuit (I2C) interface RM0444 master re-launches automatically the slave address transmission until ACK is received. In this case ADDRCF must be set if a NACK is received from the slave, in order to stop sending the slave address. If the I2C is addressed as a slave (ADDR=1) while the START bit is set, the I2C switches to slave mode and the START bit is cleared, when the ADDRCF bit is set.
Page 953: Figure 300. 10-Bit Address Read Access With Head10R=1
RM0444 Inter-integrated circuit (I2C) interface • If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this case the master sends this sequence: ReStart + Slave address 10-bit header Read.
Page 954: Figure 301. Transfer Sequence Flowchart For I2C Master Transmitter For N≤255 Bytes
Inter-integrated circuit (I2C) interface RM0444 Figure 301. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes Master transmission Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set I2C_CR2.START I2C_ISR.TXIS I2C_ISR.NACKF = Write I2C_TXDR NBYTES transmitted?
Page 955: Figure 302. Transfer Sequence Flowchart For I2C Master Transmitter For N>255 Bytes
RM0444 Inter-integrated circuit (I2C) interface Figure 302. Transfer sequence flowchart for I2C master transmitter for N>255 bytes Master transmission Master initialization NBYTES = 0xFF; N=N-255 RELOAD = 1 Configure slave address Set I2C_CR2.START I2C_ISR.TXIS I2C_ISR.NACKF = 1? = 1? Write I2C_TXDR NBYTES transmitted I2C_ISR.TC...
Page 956: Figure 303. Transfer Bus Diagrams For I2C Master Transmitter
Inter-integrated circuit (I2C) interface RM0444 Figure 303. Transfer bus diagrams for I2C master transmitter Example I2C master transmitter 2 bytes, automatic end mode (STOP) legend: TXIS TXIS transmission reception Address data1 data2 SCL stretch INIT EV1 EV2 NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: TXIS ISR: wr data1 EV2: TXIS ISR: wr data2 Example I2C master transmitter 2 bytes, software end mode (RESTART)
Page 957 RM0444 Inter-integrated circuit (I2C) interface Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2C_CR1 register.
Page 958: Figure 304. Transfer Sequence Flowchart For I2C Master Receiver For N≤255 Bytes
Inter-integrated circuit (I2C) interface RM0444 Figure 304. Transfer sequence flowchart for I2C master receiver for N≤255 bytes Master reception Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set I2C_CR2.START I2C_ISR.RXNE Read I2C_RXDR NBYTES received? I2C_ISR.TC =...
Page 959: Figure 305. Transfer Sequence Flowchart For I2C Master Receiver For N >255 Bytes
RM0444 Inter-integrated circuit (I2C) interface Figure 305. Transfer sequence flowchart for I2C master receiver for N >255 bytes Master reception Master initialization NBYTES = 0xFF; N=N-255 RELOAD =1 Configure slave address Set I2C_CR2.START I2C_ISR.RXNE Read I2C_RXDR NBYTES received? I2C_ISR.TC = Set I2C_CR2.START with slave addess NBYTES ...
Page 960: Figure 306. Transfer Bus Diagrams For I2C Master Receiver
Inter-integrated circuit (I2C) interface RM0444 Figure 306. Transfer bus diagrams for I2C master receiver Example I2C master receiver 2 bytes, automatic end mode (STOP) RXNE RXNE legend: transmission Address data1 data2 reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2 Example I2C master receiver 2 bytes, software end mode (RESTART)
Page 961: I2C_Timingr Register Configuration Examples
RM0444 Inter-integrated circuit (I2C) interface 32.4.11 I2C_TIMINGR register configuration examples The tables below provide examples of how to program the I2C_TIMINGR to obtain timings compliant with the I C specification. In order to get more accurate configuration values, the STM32CubeMX tool (I2C Configuration window) must be used. Table 168.
Page 962: Smbus Specific Features
Inter-integrated circuit (I2C) interface RM0444 2. t minimum value is 4 x t = 250 ns. Example with t = 1000 ns. SYNC1 + SYNC2 I2CCLK SYNC1 + SYNC2 minimum value is 4 x t = 250 ns. Example with t = 750 ns.
Page 963 RM0444 Inter-integrated circuit (I2C) interface Bus protocols There are eleven possible command protocols for any given device. A device may use any or all of the eleven protocols to communicate. The protocols are Quick Command, Send Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block Read, Block Write and Block Write-Block Read Process Call.
Page 964: Table 171. Smbus Timeout Specifications
Inter-integrated circuit (I2C) interface RM0444 Packet error checking A packet error checking mechanism has been introduced in the SMBus specification to improve reliability and communication robustness. Packet Error Checking is implemented by appending a Packet Error Code (PEC) at the end of each message transfer. The PEC is calculated by using the C(x) = x + x + 1 CRC-8 polynomial on all the message bytes (including addresses and read/write bits).
Page 965: Smbus Initialization
RM0444 Inter-integrated circuit (I2C) interface Figure 307. Timeout intervals for t LOW:SEXT LOW:MEXT Start Stop LOW:SEXT LOW:MEXT LOW:MEXT LOW:MEXT SMBCLK SMBDAT MS19866V1 Bus idle detection A master can assume that the bus is free if it detects that the clock and data signals have been high for t greater than t .
Page 966: Table 172. Smbus With Pec Configuration
Inter-integrated circuit (I2C) interface RM0444 Specific address (Slave mode) The specific SMBus addresses must be enabled if needed. Refer to Bus idle detection on page 965 for more details. • The SMBus Device Default Address (0b1100 001) is enabled by setting the SMBDEN bit in the I2C_CR1 register.
Page 967: Smbus: I2C_Timeoutr Register Configuration Examples
RM0444 Inter-integrated circuit (I2C) interface for a master. As the standard specifies only a maximum, the user can choose LOW:MEXT the same value for the both. Then the timer is enabled by setting the TEXTEN bit in the I2C_TIMEOUTR register. If the SMBus peripheral performs a cumulative SCL stretch for a time greater than (TIMEOUTB+1) x 2048 x t , and in the timeout interval described in...
Page 968: Smbus Slave Mode
Inter-integrated circuit (I2C) interface RM0444 • Configuring the maximum duration of t to 50 µs IDLE Table 175. Examples of TIMEOUTA settings for various I2CCLK frequencies (max t = 50 µs) IDLE TIMEOUTA[11:0] bits TIDLE bit TIMEOUTEN bit I2CCLK TIDLE 8 MHz 0x63 100 x 4 x 125 ns = 50 µs...
Page 969: Figure 308. Transfer Sequence Flowchart For Smbus Slave Transmitter N Bytes + Pec
RM0444 Inter-integrated circuit (I2C) interface Figure 308. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC SMBus slave transmission Slave initialization I2C_ISR.ADDR = Read ADDCODE and DIR in I2C_ISR stretched I2C_CR2.NBYTES = N + 1 PECBYTE=1 Set I2C_ICR.ADDRCF I2C_ISR.TXIS Write I2C_TXDR.TXDATA MS19867V2...
Page 970 Inter-integrated circuit (I2C) interface RM0444 SMBus Slave receiver When the I2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the reload mode must be selected (RELOAD=1).
Page 971: Figure 310. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec
RM0444 Inter-integrated circuit (I2C) interface Figure 310. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC SMBus slave reception Slave initialization I2C_ISR.ADDR = Read ADDCODE and DIR in I2C_ISR stretched I2C_CR2.NBYTES = 1, RELOAD =1 PECBYTE=1 Set I2C_ICR.ADDRCF I2C_ISR.RXNE =1? I2C_ISR.TCR = 1? Read I2C_RXDR.RXDATA...
Page 972: Figure 311. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
Inter-integrated circuit (I2C) interface RM0444 Figure 311. Bus transfer diagrams for SMBus slave receiver (SBC=1) legend: Example SMBus slave receiver 2 bytes + PEC transmission ADDR RXNE RXNE RXNE reception Address data1 data2 SCL stretch NBYTES EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF EV2: RXNE ISR: rd data1 EV3: RXNE ISR: rd data2 EV4: RXNE ISR: rd PEC...
Page 973: Figure 312. Bus Transfer Diagrams For Smbus Master Transmitter
RM0444 Inter-integrated circuit (I2C) interface When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the I2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low.
Page 974 Inter-integrated circuit (I2C) interface RM0444 SMBus Master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit. In this case, after NBYTES-1 data have been received, the next received byte is automatically checked versus the I2C_PECR register content.
Page 975: Figure 313. Bus Transfer Diagrams For Smbus Master Receiver
RM0444 Inter-integrated circuit (I2C) interface Figure 313. Bus transfer diagrams for SMBus master receiver Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP) RXNE RXNE RXNE legend: transmission data1 data2 Address reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2 EV3: RXNE ISR: rd PEC...
Page 976: Wakeup From Stop Mode On Address Match
Inter-integrated circuit (I2C) interface RM0444 32.4.16 Wakeup from Stop mode on address match This section is relevant only when Wakeup from Stop mode feature is supported. Refer to Section 32.3: I2C implementation. The I2C is able to wakeup the MCU from Stop mode (APB clock is off), when it is addressed.
Page 977 RM0444 Inter-integrated circuit (I2C) interface Arbitration lost (ARLO) An arbitration loss is detected when a high level is sent on the SDA line, but a low level is sampled on the SCL rising edge. • In master mode, arbitration loss is detected during the address phase, data phase and data acknowledge phase.
Page 978: Dma Requests
Inter-integrated circuit (I2C) interface RM0444 When a timeout violation is detected in master mode, a STOP condition is automatically sent. When a timeout violation is detected in slave mode, SDA and SCL lines are automatically released. When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Page 979: Debug Mode
RM0444 Inter-integrated circuit (I2C) interface DMA must be initialized before setting the START bit. The end of transfer is managed with the NBYTES counter. • In slave mode with NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in the ADDR interrupt subroutine, before clearing the ADDR flag.
Page 980: I2C Interrupts
Inter-integrated circuit (I2C) interface RM0444 32.6 I2C interrupts The table below gives the list of I2C interrupt requests. Table 177. I2C Interrupt requests Exit the Exit the Exit the Interrupt Interrupt Event Enable Interrupt clear Sleep Stop Standby acronym event flag control bit method...
Page 981: I2C Registers
RM0444 Inter-integrated circuit (I2C) interface 32.7 I2C registers Refer to Section 1.2 on page 53 for a list of abbreviations used in register descriptions. The peripheral registers are accessed by words (32-bit). 32.7.1 I2C control register 1 (I2C_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing.
Page 982 Inter-integrated circuit (I2C) interface RM0444 Bit 19 GCEN: General call enable 0: General call disabled. Address 0b00000000 is NACKed. 1: General call enabled. Address 0b00000000 is ACKed. Bit 18 WUPEN: Wakeup from Stop mode enable 0: Wakeup from Stop mode disable. 1: Wakeup from Stop mode enable.
Page 983 RM0444 Inter-integrated circuit (I2C) interface Bit 7 ERRIE: Error interrupts enable 0: Error detection interrupts disabled 1: Error detection interrupts enabled Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT) Bit 6 TCIE: Transfer Complete interrupt enable...
Page 984: I2C Control Register 2 (I2C_Cr2)
Inter-integrated circuit (I2C) interface RM0444 32.7.2 I2C control register 2 (I2C_CR2) Address offset: 0x04 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 985 RM0444 Inter-integrated circuit (I2C) interface Bit 15 NACK: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. 0: an ACK is sent after current received byte.
Page 986 Inter-integrated circuit (I2C) interface RM0444 Bit 11 ADD10: 10-bit addressing mode (master mode) 0: The master operates in 7-bit addressing mode, 1: The master operates in 10-bit addressing mode Note: Changing this bit when the START bit is set is not allowed. Bit 10 RD_WRN: Transfer direction (master mode) 0: Master requests a write transfer.
Page 987: I2C Own Address 1 Register (I2C_Oar1)
RM0444 Inter-integrated circuit (I2C) interface 32.7.3 I2C own address 1 register (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 988: I2C Own Address 2 Register (I2C_Oar2)
Inter-integrated circuit (I2C) interface RM0444 32.7.4 I2C own address 2 register (I2C_OAR2) Address offset: 0x0C Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 989: I2C Timing Register (I2C_Timingr)
RM0444 Inter-integrated circuit (I2C) interface 32.7.5 I2C timing register (I2C_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 Access: No wait states PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period t used for PRESC data setup and hold counters (refer to...
Page 990: I2C Timeout Register (I2C_Timeoutr)
Inter-integrated circuit (I2C) interface RM0444 32.7.6 I2C timeout register (I2C_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 991: I2C Interrupt And Status Register (I2C_Isr)
RM0444 Inter-integrated circuit (I2C) interface 32.7.7 I2C interrupt and status register (I2C_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIME BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS Bits 31:24 Reserved, must be kept at reset value.
Page 992 Inter-integrated circuit (I2C) interface RM0444 Bit 11 PECERR: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.
Page 993: I2C Interrupt Clear Register (I2C_Icr)
RM0444 Inter-integrated circuit (I2C) interface Bit 2 RXNE: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0.
Page 994: I2C Pec Register (I2C_Pecr)
Inter-integrated circuit (I2C) interface RM0444 Bit 10 OVRCF: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register. Bit 9 ARLOCF: Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. Bit 8 BERRCF: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
Page 995: I2C Receive Data Register (I2C_Rxdr)
RM0444 Inter-integrated circuit (I2C) interface 32.7.10 I2C receive data register (I2C_RXDR) Address offset: 0x24 Reset value: 0x0000 0000 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 996: I2C Register Map
Inter-integrated circuit (I2C) interface RM0444 32.7.12 I2C register map The table below provides the I2C register map and reset values. Table 178. I2C register map and reset values Register Offset name I2C_CR1 DNF[3:0] Reset value I2C_CR2 NBYTES[7:0] SADD[9:0] Reset value I2C_OAR1 OA1[9:0] Reset value...
Page 997 RM0444 Inter-integrated circuit (I2C) interface Table 178. I2C register map and reset values (continued) Register Offset name I2C_TXDR TXDATA[7:0] 0x28 Reset value Refer to Section 2.2 on page 58 for the register boundary addresses. RM0444 Rev 5 997/1390...
Page 998: Universal Synchonous Receiver Transmitter (Usart)
Universal synchonous receiver transmitter (USART) RM0444 Universal synchonous receiver transmitter (USART) This section describes the universal synchronous asynchronous receiver transmitter (USART). 33.1 USART introduction The USART offers a flexible means to perform Full-duplex data exchange with external equipments requiring an industry standard NRZ asynchronous serial data format. A very wide range of baud rates can be achieved through a fractional baud rate generator.
Page 999: Usart Main Features
RM0444 Universal synchonous receiver transmitter (USART) 33.2 USART main features • Full-duplex asynchronous communication • NRZ standard format (mark/space) • Configurable oversampling method by 16 or 8 to achieve the best compromise between speed and clock tolerance • Baud rate generator systems •...
Page 1000: Usart Extended Features
Universal synchonous receiver transmitter (USART) RM0444 33.3 USART extended features • LIN master synchronous break send capability and LIN slave break detection capability – 13-bit break generation and 10/11 bit break detection when USART is hardware configured for LIN • IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode •...

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