Figure 485. Dithering Principle; Figure 486. Data Format And Register Coding In Dithering Mode - ST STM32G4 Series Reference Manual

RM0440
Average period
When the dithering mode is enabled, the register coding is changed as following (see
Figure 486
•
the 4 LSBs are coding for the enhanced resolution part (fractional part)
• The MSBs are left-shifted to the bits 19:4 and are coding for the base value
Note: The ARR values will be updated automatically if the DITHEN bit is set / reset (for instance, if
ARR= 0x05 with DITHEN=0, it will be updated to ARR = 0x50 with DITHEN = 1).The
following sequence must be followed when resetting the DITHEN bit:
1. CEN and ARPE bits must be reset
2. The ARR[3:0] bits must be reset
3. The DITHEN bit must be reset
4. The CEN bit can be set ( eventually with ARPE = 1)

Figure 486. Data format and register coding in dithering mode

Register format in
dithering mode
Example

Figure 485. Dithering principle

12
T = 12
13
T = 12+¼
13
T = 12+½
13
T = 12+¾
13
T = 13
for example):
b19
MSB: 16-bits, integer part
b19
Base compare value is 20 during 16 periods
12
12
12
13
13
326
20
RM0440 Rev 1
Basic timers (TIM6/TIM7)
12 12
12 12
13 12
13
13
LSB: 4-bits
fractional part
6
Additional 6 cycles are spread over the
16 periods
12
13
MSv47466V1
b0
b0
MSv45753V2
1409/2083
1417