Figure 641. Master Clock Generation - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32G4 Series:

Table of Contents

Inter-integrated circuit (I2C) interface

SCL high level detected

SCL released

SCL high level detected

SCLH counter starts

In order to be I

Figure 641. Master clock generation

SCL master clock generation

SCLH counter starts

SCL low level detected

SCLL counter starts

SCL driven low

SCL master clock synchronization

SCL driven low by

another device

SCL low level detected

SCLL counter starts

C or SMBus compliant, the master clock must respect the timings given

SCL high level detected

SCLH counter starts

SCL low level detected

SCLL counter starts

SCL released

RM0440 Rev 1

SCL high level detected

SCLH counter starts

SCL driven low by

another device

Table of Contents

Do you have a question about the STM32G4 Series and is the answer not in the manual?