Figure 230. Early Turn-On And Early Turn-Off Behavior In "Greater Than" Pwm Mode - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus
Hide thumbs Also See for STM32G4 Series:
Table of Contents

Advertisement

RM0440
1.
In the fixed frequency configuration, the period event must trigger the output set and
the "greater than" compare triggers the output reset (or vice versa the period must
trigger the reset if the "greater-than" compare triggers the set).
2.
For variable frequency configuration, the event selected as counter reset source must
also be selected as set or reset source for the timer output (opposite direction as the
"greater than" compare event).
Note:
The "greater-than" modes must not be used when the CMP1 and/or CMP3 modes are
controlled by hardware in half and interleaved modes.

Figure 230. Early turn-ON and early turn-OFF behavior in "greater than" PWM mode

Output (GTCMP1 = 1)
(set on period, reset on CMP1)
« Greater than » PWM mode
Output (GTCMP1 = 0)
(set on period, reset on CMP1)
Regular PWM mode
The immediate update mode implies that the content of the preload register is transferred
into the active register at the very same time the register is written. When GTCMP1 and/or
GTCMP3 bits are set, their respective preload mechanism is disabled (for
HRTIM_TIMxCMP1 and/or HRTIM_TIMxCMP3 registers), whatever the PREEN bit value.
Note:
The compare interrupt flags (CMP1 and CMP3 in HRTIM_TIMxISR) are not generated in
case of late turn-ON and early turn-OFF, as shown on
Note:
The "Greater than" comparison must not be done on both CMP1 and CMP3 for the same
output (GTCMP1 and GTCMP3 bits must not be set simultaneously).
26.3.13
Events propagation within or across multiple timers
The HRTIM offers many possibilities for cascading events or sharing them across multiple
timing units, including the master timer, to get full benefits from its modular architecture.
These are key features for converters requiring multiple synchronized outputs.
This section summarizes the various options and specifies whether and how an event is
propagated within the HRTIM.
Counter
CMP1
Early turn-On
CMP1
flag set
Update on roll-over
CMP1
flag set
Write access to
CMP1
Early turn-Off
flag set
flag set
RM0440 Rev 1
High-resolution timer (HRTIM)
Write access to
Write access to
CMP1
CMP1
CMP1
flag set
CMP1
CMP1
flag set
Figure
230.
CMP1
MSv48376V1
867/2083
1040

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32G4 Series and is the answer not in the manual?

Table of Contents

Save PDF