Figure 17.27 Trs Bit Set Timing In Slave Mode - Renesas H8S/2158 User Manual

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Section 17 I C Bus Interface (IIC)
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 17.27.
To release the SCL low level that is held by means of the wait function in slave mode, clear the
TRS bit to and then dummy-read ICDR.
(a)
SDA
8 9
SCL
Data
TRS
transmission
TRS bit setting
The rise of the 9th clock is detected
13. Note on ICDR read in transmit mode and ICDR write in receive mode
When ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS =
0), the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly.
To access ICDR correctly, read the ICDR after setting receive mode or write to the ICDR after
setting transmit mode.
14. Note on ACKE and TRS bits in slave mode
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In the I C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
address does not match.
Similarly, if the start condition or address is transmitted from the master device in slave
transmit mode (TRS = 1) and 1 is received as the acknowledge bit value (ACKB = 1), the IRIC
flag may be set thus causing an interrupt source even when the address does not match.
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To use the I C bus interface module in slave mode, be sure to follow the procedures below.
Rev. 3.00 Jan 25, 2006 page 548 of 872
REJ09B0286-0300
Restart condition
1 2
Address reception
TRS bit setting is suspended in this period
ICDR dummy read

Figure 17.27 TRS Bit Set Timing in Slave Mode

(b)
3 4 5 6 7
The rise of the 9th clock is detected
A
8 9