Bit Synchronous Circuit; Figure 17.18 Timing Of Bit Synchronous Circuit; Table 17.4 Time For Monitoring Scl - Renesas H8S/2437 Hardware Manual

17.6

Bit Synchronous Circuit

In master mode,
• When the SCL is driven low by the slave device
• When the rising speed of the SCL is lower by the load of the SCL line (load capacitance or
pull-up resistance)
This module has a possibility that the high level period may be short in the two states described
above. Therefore it monitors the SCL and communicates by bits with synchronization.
Figure 17.18 shows the timing of the bit synchronous circuit and table 17.4 shows the time when
SCL output changes from low to Hi-Z then the SCL is monitored.
Reference clock
for SCL monitor
timing
SCL
Internal SCL

Table 17.4 Time for Monitoring SCL

CKS3 CKS2
0 0
1
1 0
1
Rev. 1.00, 09/03, page 506 of 704
VIH

Figure 17.18 Timing of Bit Synchronous Circuit

Time for Monitoring SCL
7.5 tcyc
19.5 tcyc
17.5 tcyc
41.5 tcyc