Usage Notes; Issue (Retransmission) Of Start/Stop Conditions; Wait Setting In I; C Bus Mode Register (Icmr) - Renesas H8 Series Hardware Manual

2
Section 15 I C Bus Interface 2 (IIC2)
SCL monitor
timing reference
clock
SCL
Internal SCL

Figure 15.21 The Timing of the Bit Synchronous Circuit

Table 15.4 Time for Monitoring SCL

CKS3 CKS2
0 0
1
1 0
1
15.7

Usage Notes

15.7.1

Issue (Retransmission) of Start/Stop Conditions

In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing
under the following condition 1 or 2, such conditions may not be output successfully. To avoid
this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check
the SCLO bit in the I
1. When the rising of SCL falls behind the time specified in section 15.6, Bit Synchronous
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth
clocks, that is driven by the slave device
15.7.2

WAIT Setting in I

If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the
slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To
avoid this, set the WAIT bit in ICMR to 0.
Rev. 1.00 Aug. 28, 2006 Page 274 of 400
REJ09B0268-0100
Time for Monitoring SCL
7.5 tcyc
19.5 tcyc
17.5 tcyc
41.5 tcyc
2
C control register 2 (IICR2) to confirm the fall of the ninth clock.
2

C Bus Mode Register (ICMR)

VIH