18.10 Automatically Low-Hold Function For Scl; Function To Prevent Wrong Transmission Of Transmit Data - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

18.10 Automatically Low-Hold Function for SCL

18.10.1

Function to Prevent Wrong Transmission of Transmit Data

If the shift register (RIICnDRS) is empty when data have not been written to the transmit data register
(RIICnDRT) with the RIIC in transmission mode (RIICnCR2.TRS bit = 1), the SCL signal is
automatically held at the low level over the intervals shown below. This low-hold period is extended
until data for transmission have been written, which prevents the unintended transmission of erroneous
data.
<Master transmit mode>
• Low-level interval after a start condition or restart condition is issued
• Low-level interval of one clock cycle between the ninth clock cycle of one transfer and the first
clock cycle of the next
<Slave transmit mode>
• Low-level interval between the ninth clock cycle of one transfer and the first clock cycle of the
next
[Master transmit mode]
SCLn
SDAn
BBSY
AASy
TRS
TDRE
RDRF
[Slave transmit mode]
SCLn
SDAn
BBSY
AASy
TRS
TDRE
RDRF
Figure 18.30
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Automatic low-hold (to prevent wrong transmission)
S 1 2 3 4 5
7-bit slave address
Transmit data (7-bit address + W)
Write data to RIICnDRT
(7-bit address + W)
S 1 2 3 4 5 6
7-bit slave address
Automatic Low-Hold Operation in Transmit Mode
Automatic low-hold (to prevent wrong transmission)
6 7 8 9 1 2
W ACK
Transmit data (DATA 1)
Write data to RIICnDRT
(DATA 1)
Automatic low-hold (to prevent wrong transmission)
7 8 9 1 2 3
Data (DATA 1)
R ACK
Address match
Transmit data (DATA 1)
Write data to RIICnDRT
(DATA 1)
18. I²C Bus Interface
3 4 5 6 7 8 9
Data (DATA 1)
ACK
Transmit data (DATA 2)
Write data to RIICnDRT
(DATA 2)
Automatic low-hold
(to prevent wrong
transmission)
4 5 6 7 8 9
ACK
Transmit data (DATA 2)
Write data to RIICnDRT
(DATA 2)
Automatic low-hold
(to prevent wrong
transmission)
1 2
1 2 3
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