Table 17.12 Permissible Scl Rise Time - Renesas H8S/2158 User Manual

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Section 17 I C Bus Interface (IIC)
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5. The I C bus interface specification for the SCL rise time t
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 17.12.
Table 17.12 Permissible SCL Rise Time (t
IICX1, t
cyc
IICX0 Indication
0 7.5 t Standard mode
cyc
High-speed mode 300
1 17.5 t Standard mode
cyc
High-speed mode 300
2
6. The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
2
and 300 ns. The I
in table 17.11. However, because of the rise and fall times, the I
may not be satisfied at the maximum transfer rate. Table 17.13 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times. The values in the above table will vary depending on the settings of the IICX1,
IICX0, and CKS2 to CKS0 bits. Depending on the frequency it may not be possible to achieve
the maximum transfer rate; therefore, whether or not the I
met must be determined in accordance with the actual setting conditions. t
2
I C bus interface specifications at any frequency. The following solutions should be
investigated.
• Provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition.
• Select devices whose input timing permits this output timing for use as slave devices
connected to the I
t in high-speed mode and t
SCLLO
specifications for worst-case calculations of t
investigated.
• Adjusting the rise and fall times by means of a pull-up resistor and capacitive load.
• Reducing the transfer rate to meet the specifications.
Rev. 3.00 Jan 25, 2006 page 542 of 872
REJ09B0286-0300
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C bus interface monitors the SCL line and synchronizes
2
I C Bus
Specification
(Max.)
1000
1000
C bus interface SCL and SDA output timing is prescribed by t
2
C bus.
STASO
is 1000 ns or less (300 ns for high-
sr
(the time for SCL to go from low to V
sr
2
C bus interface, the high period of SCL is
) Values
sr
Time Indication[ns]
φ φ φ φ = φ φ φ φ = φ φ φ φ =
5 MHz 8 MHz 10 MHz
1000 937 750
300 300 300
1000 1000 1000
300 300 300
2
C bus interface specifications are
in standard mode fail to satisfy the I
/t . The following solutions should be
Sr Sf
IH
φ φ φ φ = φ φ φ φ =
16 MHz 20 MHz
468 375
300 300
1000 875
300 300
, as shown
cyc
2
C bus interface specifications
fails to meet the
BUFO
2
C bus interface
) exceeds
φ φ φ φ =
25 MHz
300
300
700
300