Cop Watchdog Operation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Functional description

12.4.1 COP watchdog operation

The COP watchdog is intended to force a system reset when the application software fails
to execute as expected. To prevent a system reset from the COP timer (when it is
enabled), the application software must reset the COP counter periodically. If the
application program gets lost and fails to reset the COP counter before it times out, a
system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an
application, it can be disabled by clearing SIM_COPC[COPT].
The COP counter is reset by writing 0x55 and 0xAA (in that order) to the address of the
SIM's Service COP (SRVCOP) register during the selected timeout period. Writes do not
affect the data in the SRVCOP register. As soon as the write sequence is complete, the
COP timeout period is restarted. If the program fails to perform this restart during the
timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is
written to the SRVCOP register, the microcontroller immediately resets.
SIM_COPC[COPCLKS] and SIM_COPCTRL[COPCLKSEL] select the timeout
duration and clock source used for the COP timer. The clock source options are either the
bus clock, 8 MHz/2 MHz IRC, external crystal or an internal 1 kHz clock source. With
each clock source, the associated timeouts are controlled by SIM_COPC[COPT] and
SIM_COPC[COPCLKS]. The following table summarizes the control functions of
SIM_COPCTRL[COPCLKS] and SIM_COPC[COPCLKSEL] and SIM_COPC[COPT]
fields. The COP watchdog defaults to operation from the 1 kHz clock source and the
10
longest timeout is 2
SIM_COPC[COPCLK SIM_COPC[COPCLK
SEL]
N/A
00
00
00
170
cycles.
Table 12-1. COP configuration options
Control bits
SIM_COPC[COP
S]
N/A
0
1
0
1
0
1
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Clock COP window opens
source
(SIM_COPC[COPW]=1)
T]
00 N/A
01 1 kHz
10 1 kHz
11 1 kHz
COP overflow
count
N/A COP is disabled.
5
N/A 2 cycles (32ms)
13
6,144 cycles 2
(8192ms)
8
N/A 2
(256ms)
16
49,152 cycles 2
(65536ms)
10
N/A 2 cycles (1024
18
196,608 cycles 2
(262144ms)
Freescale Semiconductor, Inc.
cycles
cycles
cycles
ms)
cycles