Port Data Direction Register (Gpiox_Pddr); Functional Description; General-Purpose Input; General-Purpose Output - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Functional description

Field
PDI Port Data Input
Reads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digital
function read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR
does not update.
0 Pin logic level is logic 0, or is not configured for use by digital function.
1 Pin logic level is logic 1.

41.3.6 Port Data Direction Register (GPIOx_PDDR)

The PDDR configures the individual port pins for input or output.
Address: Base address + 14h offset
Bit 31 30 29 28 27 26
R
W
0 0 0 0 0 0
Reset
Field
PDD Port Data Direction
Configures individual port pins for input or output.
0 Pin is configured as general-purpose input, for the GPIO function.
1 Pin is configured as general-purpose output, for the GPIO function.
41.4 Functional description

41.4.1 General-purpose input

The logic state of each pin is available via the Port Data Input registers, provided the pin
is configured for a digital function and the corresponding Port Control and Interrupt
module is enabled.
828
GPIOx_PDIR field descriptions
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
GPIOx_PDDR field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
17 16 15 14 13 12 11 10
PDD
0 0 0 0 0 0 0 0
Description
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
Freescale Semiconductor, Inc.
1 0
0 0