Llwu Pin Filter 1 Register (Llwu_Filt1) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear

the flag, follow the internal peripheral flag clearing mechanism.

Module 2 input was not a wakeup source

Module 2 input was a wakeup source

Wakeup flag For module 1

Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear

the flag, follow the internal peripheral flag clearing mechanism.

Module 1 input was not a wakeup source

Module 1 input was a wakeup source

Wakeup flag For module 0

Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear

the flag, follow the internal peripheral flag clearing mechanism.

Module 0 input was not a wakeup source

Module 0 input was a wakeup source

18.4.9 LLWU Pin Filter 1 register (LLWU_FILT1)

LLWU_FILT1 is a control and status register that is used to enable/disable the digital

filter 1 features for an external pin.

This register is reset on Chip Reset not VLLS and by reset

types that trigger Chip Reset not VLLS. It is unaffected by reset

types that do not trigger Chip Reset not VLLS. See the

Introduction

Address: 4007_C000h base + 8h offset = 4007_C008h

Filter Detect Flag

Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage

power mode. To clear the flag write a one to FILTF.

Freescale Semiconductor, Inc.

LLWU_F3 field descriptions (continued)

details for more information.

LLWU_FILT1 field descriptions

Table continues on the next page...

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 18 Low-Leakage Wakeup Unit (LLWU)