Fault Protection - NXP Semiconductors freescale KV4 Series Reference Manual

Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)

37.5.2.12 Fault Protection

Fault protection can control any combination of PWM output pins. Faults are generated
by a logic one on any of the FAULTx pins. This polarity can be changed via
FCTRL[FLVL]. Each FAULTx pin can be mapped arbitrarily to any of the PWM
outputs. When fault protection hardware disables PWM outputs, the PWM generator
continues to run, only the output pins are forced to logic 0, logic 1, or tristated depending
the values of OCTRL[PWMxFS].
The fault decoder disables PWM pins selected by the fault logic and the disable mapping
(DISMAPn) registers. The following figure shows an example of the fault disable logic.
Each bank of bits in DISMAPn control the mapping for a single PWM pin. See the
following table.
The fault protection is enabled even when the PWM module is not enabled; therefore, a
fault will be latched in and must be cleared in order to prevent an interrupt when the
PWM is enabled.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc. 851