Pwm Generation - NXP Semiconductors freescale KV4 Series Reference Manual

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37.5.2.4 PWM Generation

Figure 37-237

illustrates how PWM generation is accomplished in each submodule. In

each case, two comparators and associated VALx registers are utilized for each PWM

output signal. One comparator and VALx register are used to control the turn-on edge,

while a second comparator and VALx register control the turn-off edge.

16 bit counter

The generation of the Local Sync signal is performed exactly the same way as the other

PWM signals in the submodule. While comparator 0 causes a falling edge of the Local

Sync signal, comparator 1 generates a rising edge. Comparator 1 is also hardwired to the

reload logic to generate the full cycle reload indicator.

If VAL1 is controlling the modulus of the counter and VAL0 is half of the VAL1 register

minus the INIT value, then the half cycle reload pulse will occur exactly half way

through the timer count period and the Local Sync will have a 50% duty cycle. On the

other hand, if the VAL1 and VAL0 registers are not required for register reloading or

Freescale Semiconductor, Inc.

Figure 37-237. PWM Generation Hardware

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)

to Force Out

Output Triggers