Chapter 38 Programmable Delay Block (Pdb) - NXP Semiconductors freescale KV4 Series Reference Manual

Chapter 38
Programmable Delay Block (PDB)
38.1 Chip-specific PDB information
38.1.1 PDB Instantiation
This chip has two PDBs that primarily provide delayed triggering from the FTMs to the
ADCs. Each PDB has one trigger output with four pre-trigger channels, four pulse output
and one DAC trigger. The input mux capability has been increased by having an XBARA
output trigger the PDBs.
38.1.1.1 PDB0 Output Triggers
Number of pre-triggers per PDB channel
38.1.1.2 PDB0 Input Trigger Connections
PDB Trigger
Freescale Semiconductor, Inc.
Table 38-1. PDB0 output triggers
Number of PDB channels
PDB_ch0_out
DAC trigger
PulseOut
Table 38-2. PDB0 Input Trigger Options
0000
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
ADCA sync0 , DMA_MUX
source 48, FTM0_TRIG1,
XBARA_IN29, XBARB_IN12
DAC0_trigger
Window control of CMP0,
CMP1,CMP2,CMP3
PDB Input
External Trigger (PDB0_EXTRG)
1
4
863