Asynchronous Wake-Up Interrupt Controller (Awic) Configuration - NXP Semiconductors freescale KV4 Series Reference Manual

Table 3-4. Interrupt vector assignments (continued)
Address Vector
0x0000_01B0 108
0x0000_01B4 109
0x0000_01B8 110
0x0000_01BC 111
0x0000_01C0 112
0x0000_01C4 113
0x0000_01C8 114
0x0000_01CC 115
1. Don't put the instruction to clear interrupt in last line of ISR
3.3 Asynchronous Wake-up Interrupt Controller (AWIC)
Configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at arm.com.
Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration
Table 3-5. Reference links to related information
Topic
System memory map
Clocking
Power management
Interrupt Controller
Wake-up requests
Freescale Semiconductor, Inc.
IRQ Source description
92
93
94 FLexCAN1 OR'ed Message buffer (0-15)
95 FLexCAN1 Bus Off
96 FLexCAN1 Error
97 FLexCAN1 Transmit Warning
98 FLexCAN1 Receive Warning
99 FLexCAN1 Wake Up
Asynchronous
Nested vectored
Wake-up Interrupt
interrupt controller
Controller (AWIC)
(NVIC)
Related module
Nested Vectored
(NVIC)
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
CMP3
—
Clock logic
Wake-up
requests
Module
Module
Reference
System memory map
Clock distribution
Power management
NVIC
AWIC wake-up sources
Chapter 3 Core overview
Source module
CMP3
CAN1
CAN1
CAN1
CAN1
CAN1
1
CAN1
79