Receiver Bit Ordering; Character Reception; Data Sampling - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description

46.5.2.2 Receiver bit ordering

When S2[MSBF] is set, the receiver operates such that the first bit received after the start
bit is the MSB of the dataword. Similarly, the bit received immediately preceding the
parity bit, or the stop bit if parity is not enabled, is treated as the LSB for the dataword.
All necessary bit ordering is handled automatically by the module. Therefore, the format
of the data read from receive data buffer is completely independent of S2[MSBF].

46.5.2.3 Character reception

During UART reception, the receive shift register shifts a frame in from the
unsynchronized receiver input signal. After a complete frame shifts into the receive shift
register, the data portion of the frame transfers to the UART receive buffer. Additionally,
the noise and parity error flags that are calculated during the receive process are also
captured in the UART receive buffer. The receive data buffer is accessible via the D and
C3[T8] registers. Additional received information flags regarding the receive dataword
can be read in ED register. S1[RDRF] is set if the number of resulting datawords in the
receive buffer is equal to or greater than the number indicated by RWFIFO[RXWATER].
If the C2[RIE] is also set, RDRF generates an RDRF interrupt request. Alternatively, by
programming C5[RDMAS], a DMA request can be generated.

46.5.2.4 Data sampling

The receiver samples the unsynchronized receiver input signal at the RT clock rate. The
RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud
rate mismatch, the RT clock (see the following figure) is re-synchronized:
• After every start bit.
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority
of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of
the next RT8, RT9, and RT10 samples returns a valid logic 0).
To locate the start bit, data recovery logic does an asynchronous search for a logic 0
preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT
clock begins to count to 16.
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KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.