I2C Control Register 1 (I2Cx_C1) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Memory map/register definition

The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C data).

SDA hold time = I2C module clock period (s) × mul × SDA hold value

The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start

condition) to the falling edge of SCL (I2C clock).

SCL start hold time = I2C module clock period (s) × mul × SCL start hold value

The SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C

data) while SCL is high (stop condition).

SCL stop hold time = I2C module clock period (s) × mul × SCL stop hold value

For example, if the I2C module clock speed is 8 MHz, the following table shows the possible hold time

values with different ICR and MULT selections to achieve an I

36.4.3 I2C Control Register 1 (I2Cx_C1)

Address: Base address + 2h offset

Enables I2C module operation.

I2C Interrupt Enable

Enables I2C interrupt requests.

I2Cx_F field descriptions (continued)

I2Cx_C1 field descriptions

Table continues on the next page...

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

C baud rate of 100 kbit/s.

Hold times (μs)

Freescale Semiconductor, Inc.