I2C Control Register 2 (I2C_C2) - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Memory map/register definition

The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for the

transmission to begin. For example, if the I2C module is configured for master transmit but a master

receive is desired, reading the Data register does not initiate the receive.

Reading the Data register returns the last byte received while the I2C module is configured in master

receive or slave receive mode. The Data register does not reflect every byte that is transmitted on the I2C

bus, and neither can software verify that a byte has been written to the Data register correctly by reading it

In master transmit mode, the first byte of data written to the Data register following assertion of MST (start

bit) or assertion of RSTA (repeated start bit) is used for the address transfer and must consist of the

calling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).

45.4.6 I2C Control Register 2 (I2C_C2)

Address: 4006_6000h base + 5h offset = 4006_6005h

General Call Address Enable

Enables general call address.

Address Extension

Controls the number of bits used for the slave address.

7-bit address scheme

10-bit address scheme

High Drive Select

Controls the drive capability of the I2C pads.

Normal drive mode

High drive mode

Slave Baud Rate Control

Enables independent slave mode baud rate at maximum frequency, which forces clock stretching on SCL

in very fast I2C modes. To a slave, an example of a "very fast" mode is when the master transfers at 40

kbit/s but the slave can capture the master's data at only 10 kbit/s.

The slave baud rate follows the master baud rate and clock stretching may occur

Slave baud rate is independent of the master baud rate

I2C_D field descriptions (continued)

I2C_C2 field descriptions

Table continues on the next page...

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.