I2C Status Register (I2C_S) - NXP Semiconductors freescale KV4 Series Reference Manual

Field
3 Transmit Acknowledge Enable
TXAK
Specifies the value driven onto the SDA during data acknowledge cycles for both master and slave
receivers. The value of SMB[FACK] affects NACK/ACK generation.
NOTE: SCL is held low until TXAK is written.
0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the
current receiving byte (if FACK is set).
1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or
the current receiving data byte (if FACK is set).
2 Repeat START
RSTA
Writing 1 to this bit generates a repeated START condition provided it is the current master. This bit will
always be read as 0. Attempting a repeat at the wrong time results in loss of arbitration.
1 Wakeup Enable
WUEN
The I2C module can wake the MCU from low power mode with no peripheral bus running when slave
address matching occurs.
0 Normal operation. No interrupt generated when address matching in low power mode.
1 Enables the wakeup function in low power mode.
0 DMA Enable
DMAEN
Enables or disables the DMA function.
0 All DMA signalling disabled.
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request:
• a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic)
• the first byte received matches the A1 register or is a general call address.
If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from
master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used
in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the
C1 register operation. With this assumption, DMA cannot be used.
When FACK = 1, an address or a data byte is transmitted.

45.4.4 I2C Status register (I2C_S)

Address: 4006_6000h base + 3h offset = 4006_6003h
Bit 7
Read TCF
Write
Reset 1
Freescale Semiconductor, Inc.
I2C_C1 field descriptions (continued)
6 5
BUSY ARBL
IAAS
w1c
0 0
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 45 Inter-Integrated Circuit (I2C)
Description
4 3 2
SRW
RAM
0 0 0
1 0
IICIF RXAK
w1c
0 0
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