I2C Control Register 1 (I2C_C1) - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Memory map/register definition

45.4.3 I2C Control Register 1 (I2C_C1)

Address: 4006_6000h base + 2h offset = 4006_6002h

Enables I2C module operation.

I2C Interrupt Enable

Enables I2C interrupt requests.

Master Mode Select

When MST is changed from 0 to 1, a START signal is generated on the bus and master mode is selected.

When this bit changes from 1 to 0, a STOP signal is generated and the mode of operation changes from

master to slave.

Transmit Mode Select

Selects the direction of master and slave transfers. In master mode this bit must be set according to the

type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave

this bit must be set by software according to the SRW bit in the status register.

I2C_F field descriptions (continued)

I2C_C1 field descriptions

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KV4x Reference Manual, Rev. 2, 02/2015

Hold times (μs)

Freescale Semiconductor, Inc.