Mcg Mode Switching - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Table 30-15. MCG modes of operation (continued)

Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power

mode assignments, see the chapter that describes how modules are configured and MCG behavior

during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static

except in the following case:

MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1

MCGIRCLK is active in Normal Stop mode when all the following conditions become true:

1. Caution: If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock

selected (C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG

clock mode switch to a non low power clock mode must be avoided.

For the chip-specific modes of operation, see the power

management chapter of this MCU.

30.4.1.2 MCG mode switching

C1[IREFS] can be changed at any time, but the actual switch to the newly selected

reference clocks is shown by S[IREFST]. When switching between engaged internal and

engaged external modes, the FLL will begin locking again after the switch is completed.

C1[CLKS] can also be changed at any time, but the actual switch to the newly selected

clock is shown by S[CLKST]. If the newly selected clock is not available, the previous

clock will remain selected.

The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1.

If C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL

engaged external (FEE) mode, the MCGOUTCLK switches to the new selected DCO

Freescale Semiconductor, Inc.

• C1[IRCLKEN] = 1

• C1[IREFSTEN] = 1

• In VLPS Stop Mode, the MCGIRCLK can be programmed to stay enabled and

continue running if C1[IRCLKEN] = 1, C1[IREFSTEN]=1, and Fast IRC clock is

selected (C2[IRCS] = 1)

• When entering Low Power Stop mode (VLPS) from PEE mode, on exit the MCG

clock mode is forced to PBE clock mode. C1[CLKS] and S[CLKST] will be configured

to 2'b10if entering from PEE mode or to 2'b01 if entering from PEI mode,

C5[PLLSTEN0] will be force to 1'b0 and S[LOCK] bit will be cleared without setting

• When entering Normal Stop mode from PEE mode and if C5[PLLSTEN]=0, on exit

the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be

configured to 2'b10 and S[LOCK] bit will clear without setting S[LOLS]. If

C5[PLLSTEN]=1, the S[LOCK] bit will not get cleared and on exit the MCG will

continue to run in PEE mode.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 30 Multipurpose Clock Generator (MCG)