10.10.8 Contention Between Tgr Read And Input Capture; Figure 10.48 Contention Between Buffer Register Write And Compare Match; Figure 10.49 Contention Between Tgr Read And Input Capture - Renesas H8S/2368 Series Hardware Manual

φ
Address
Write signal
Compare
match signal
Buffer
register
TGR

Figure 10.48 Contention between Buffer Register Write and Compare Match

10.10.8 Contention between TGR Read and Input Capture

If the input capture signal is generated in the T
be the data after input capture transfer.
Figure 10.49 shows the timing in this case.
φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus

Figure 10.49 Contention between TGR Read and Input Capture

Rev. 2.00, 05/03, page 448 of 820
TGR write cycle
T T
1 2
Buffer register
address
N M
N
state of a TGR read cycle, the data that is read will
1
TGR read cycle
T T
1 2
TGR address
X M
M
Buffer register write data