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Section 10 16-Bit Timer Pulse Unit (TPU)
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR
Figure 10.47 Conflict between Buffer Register Write and Compare Match
10.8.7
Conflict between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer. Figure 10.48 shows the timing in this case.
φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus
Figure 10.48 Conflict between TGR Read and Input Capture
Rev. 1.00 Apr. 28, 2008 Page 300 of 994
REJ09B0452-0100
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N
M
N
TGR read cycle
T1
T2
TGR address
X
M
M
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