Contention Between Buffer Register Write And Tcnt Clear; Contention Between Tgr Read And Input Capture - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.7.8

Contention between Buffer Register Write and TCNT Clear

When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear
occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before
write.
Figure 10.103 shows the timing in this case.
P0φ
Address
Write signal
TCNT clear
signal
Buffer transfer
signal
Buffer register
TGR
Figure 10.103 Contention between Buffer Register Write and TCNT Clear
10.7.9

Contention between TGR Read and Input Capture

If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the
buffer before input capture transfer.
Figure 10.104 shows the timing in this case.
Figure 10.104 Contention between TGR Read and Input Capture
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
P0φ
Address
Read signal
Input capture
signal
N
TGR
Internal data
bus
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N M
N
TGR read cycle
T1 T2
TGR address
M
N
10. Multi-Function Timer Pulse Unit 2
10-145