Contention Between Tgr Read And Input Capture; Figure 10.49 Contention Between Tgr Read And Input Capture - Renesas H8S Series Hardware Manual

10.9.8

Contention between TGR Read and Input Capture

If an input capture signal is generated in the T
be that in the buffer after input capture transfer.
Figure 10.49 shows the timing in this case.
φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus

Figure 10.49 Contention between TGR Read and Input Capture

Section 10 16-Bit Timer Pulse Unit (TPU)
state of a TGR read cycle, the data that is read will
1
TGR read cycle
T T
1 2
TGR address
X M
M
Rev. 6.00 Mar 15, 2006 page 239 of 570
REJ09B0211-0600