I2C Address Register 1 (I2Cx_A1); I2C Frequency Divider Register (I2Cx_F) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

36.4.1 I2C Address Register 1 (I2Cx_A1)

This register contains the slave address to be used by the I2C module.
Address: Base address + 0h offset
Bit 7
Read
Write
Reset
0
Field
7–1 Address
AD[7:1]
Contains the primary slave address used by the I2C module when it is addressed as a slave. This field is
used in the 7-bit address scheme and the lower seven bits in the 10-bit address scheme.
0 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

36.4.2 I2C Frequency Divider register (I2Cx_F)

Address: Base address + 1h offset
Bit 7
Read
MULT
Write
Reset 0
Field
7–6 Multiplier Factor
MULT
Defines the multiplier factor (mul). This factor is used along with the SCL divider to generate the I2C baud
rate.
00 mul = 1
01 mul = 2
10 mul = 4
11 Reserved
ICR ClockRate
Prescales the I2C module clock for bit rate selection. This field and the MULT field determine the I2C baud
rate, the SDA hold time, the SCL start hold time, and the SCL stop hold time. For a list of values
corresponding to each ICR setting, see
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate.
I2C baud rate = I2C module clock speed (Hz)/(mul × SCL divider)
Freescale Semiconductor, Inc.
6 5
AD[7:1]
0 0
I2Cx_A1 field descriptions
6 5
0 0
I2Cx_F field descriptions
I2C divider and hold
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 36 Inter-Integrated Circuit (I2C)
4 3
0 0
Description
4 3
ICR
0 0
Description
values.
2 1
0 0
2 1
0 0
0
0
0
0
0
615