Cmp Interrupts; Cmp Asynchronous Dma Support - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

CMP interrupts

represents the intrinsic delay of the analog component plus the polarity select logic. T

external sample clock. T

35.5 CMP interrupts

The CMP module is capable of generating an interrupt on either the rising- or falling-

edge of the comparator output, or both.

The following table gives the conditions in which the interrupt request is asserted and

SCR[IER] and SCR[CFR] are set

SCR[IEF] and SCR[CFF] are set

SCR[IER] and SCR[CFR] are cleared for a rising-edge

SCR[IEF] and SCR[CFF] are cleared for a falling-edge

35.6 DMA support

Normally, the CMP generates a CPU interrupt if there is a change on the COUT. When

DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting

SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA

transfer request rather than a CPU interrupt instead. When the DMA has completed the

transfer, it sends a transfer completing indicator that deasserts the DMA transfer request

and clears the flag to allow a subsequent change on comparator output to occur and force

another DMA request.

The comparator can remain functional in STOP modes.

When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by

setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA

transfer request to wake up the system from STOP modes. After the data transfer has

finished, system will go back to STOP modes. Refer to DMA chapters in the device

reference manual for the asynchronous DMA function for details.

The comparator can remain functional in STOP modes.

is the period of the bus clock.

KV4x Reference Manual, Rev. 2, 02/2015

The interrupt request is asserted

The interrupt request is deasserted

is the clock period of the

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