On-Chip Supporting Module Access Timing; Usage Note - Renesas Hitachi H8S/2194 Series Hardware Manual

2.9.3

On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16
bits wide, depending on the particular internal I/O register being accessed. Figure 2.18 shows
the access timing for the on-chip supporting modules.
Internal address bus
Internal read signal
Read access
Internal data bus
Internal write signal
Write access
Internal data bus
Figure 2.18 On-Chip Supporting Module Access Cycle
2.10

Usage Note

Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Hitachi H8S or H8/300 series C/C++ compilers. If the TAS
instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4,
or ER5 is used.
Rev. 2.0, 11/00, page 58 of 1037
Bus cycle
T1
Address
Read data
Write data
T2