On-Chip Supporting Module Access Timing - Renesas H8S/2319 series Hardware Manual

2.9.3

On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2-16 shows the
access timing for the on-chip supporting modules. Figure 2-17 shows the pin states.
φ
Internal address bus
Internal read signal
Read
access
Internal data bus
Internal write signal
Write
access
Internal data bus
Figure 2-16 On-Chip Supporting Module Access Cycle
Rev. 5.00, 12/03, page 66 of 1088
Bus cycle
T
1
Address
Read data
Write data
T
2