On-Chip Supporting Module Access Timing - Renesas H8S Series Hardware Manual

2.9.3

On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the
particular internal I/O register being accessed. Figure 2-16 shows the access timing for the on-chip supporting modules.
Figure 2-17 shows the pin states.
ø
Internal address bus
Read
access
Write
access
Rev.6.00 Oct.28.2004 page 52 of 1016
REJ09B0138-0600H
ø
Address bus
AS
RD
HWR, LWR
Data bus
Figure 2-15 Pin States during On-Chip Memory Access
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Figure 2-16 On-Chip Supporting Module Access Cycle
Bus cycle
T
1
Unchanged
High
High
High
High-impedance state
Bus cycle
T
1
Address
T
2
Read data
Write data