On-Chip Support Module Access Timing; Figure 7.2 On-Chip Support Module Access Cycle - Renesas H8S Series Hardware Manual

Section 7 Bus Controller
7.1.2

On-Chip Support Module Access Timing

The on-chip support modules, except for HCAN, MMT, and POE, are accessed in two states. The
data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being
accessed. For details, refer to appendix A, On-Chip I/O Register. Figure 7.2 shows access timing
for the on-chip supporting modules.
φ
Internal address bus
Read
access
Write
access
Rev. 6.00 Mar 15, 2006 page 98 of 570
REJ09B0211-0600
Internal read signal
Internal data bus
Internal write signal
Internal data bus

Figure 7.2 On-Chip Support Module Access Cycle

Bus cycle
T T
1 2
Address
Read data
Write data