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17.3
Operations
17.3.1
Power-On Reset Circuit
Figure 17.3 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the internal pull-up resistor (Typ. 150 kΩ). While the RES signal is driven low, the prescaler S and
the entire chip retains the reset state. When the level on the RES signal reaches the specified value,
the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to
release the internal reset signal after the prescaler S has counted 131,072 cycles of the φ clock. The
noise filter circuit which removes noise with less than 400 ns (Typ.) is included to prevent the
incorrect operation of this LSI caused by noise on the RES signal.
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle
(t
) is determined by the oscillation frequency (f
PWON
RES pin (C
). Where t
RES
the power supply, the power supply circuit should be designed to satisfy the following formula.
t
PWON
(t
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV to remove charge on the
RES pin. After that, it can be risen. To remove charge on the RES pin, it is recommended that the
diode should be placed to Vcc. If the power supply voltage (Vcc) rises from the point above Vpor,
a power-on reset may not occur.
Vcc
Vpor
PSS-reset
signal
OVF
Internal reset
signal
Rev. 1.00, 11/03, page 272 of 376
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is assumed to be the time required to reach 90 % of the full level of
PWON
(ms) ≤ 90 × C
(µF) + 162/f
RES
≤ 3000 ms, C
RES
PWON
t
PWON
131,072 cycles
PSS counter starts
Figure 17.3 Operational Timing of Power-On Reset Circuit
) and capacitance which is connected to
OSC
(MHz)
OSC
≥ 0.22 µF, and f
= 10 in 2-MHz to 10-MHz operation)
OSC
Reset released
Vss
Vss
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