Basic Operational Timing; Access To On-Chip Memory (Ram, Rom) - Renesas H8/38024 Hardware Manual

2.6

Basic Operational Timing

CPU operation is synchronized by a system clock (φ) or a subclock (φ
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1

Access to On-Chip Memory (RAM, ROM)

Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
φ or φ
SUB
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Rev. 6.00, 08/04, page 54 of 628
T state
1
Figure 2.11 On-Chip Memory Access Cycle
). For details on these
SUB
Bus cycle
T state
2
Address
Read data
Write data
to
SUB